AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 40

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
Table 30. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
Table 31. Channel Divider Output Duty Cycle When the
VCO Divider Is Enabled and Set to 1
Input
Clock
Duty Cycle
Any
50%
X%
Note that the channel divider must be enabled when the VCO
divider = 1.
Table 32. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
Any
Any
50%
X%
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
Even
Odd
Even
Odd
N + M + 2
Even
Odd
Odd
N + M + 2
Channel
divider
bypassed
Even
Odd
Odd
D
X
D
D
X
X
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
Disable Div
DCC = 1
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Disable Div
DCC = 1
Same as input
duty cycle
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Disable Div DCC = 0
50%
(1 + X%)/3
(2 + X%)/5
50%, requires M = N
50%, requires M = N + 1
50%, requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%, requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Disable Div DCC = 0
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Disable Div DCC = 0
Same as input duty
cycle
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Rev. 0 | Page 40 of 76
Divider
0
1
2
3
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 33).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs—SYNC Function
section).
Table 33. Setting Phase Offset and Division
Let
Δ
Δ
T
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δ
Δ
Case 2
For Φ ≥ 16,
Δ
Δ
t
c
X
t
c
t
c
= delay (in seconds).
= Φ × T
= (Φ − 16 + M + 1) × T
= delay (in cycles of clock signal at input to D
= Δ
= Δ
= period of the clock signal at the input of the divider, D
t
t
/T
/T
X
X
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
0x19A[4]
X
= Φ
0x19A[3:0]
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
X
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
X
).
0x199[3:0]
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
X
(in