AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 65

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01B
01B
01B
01B
[7]
[6]
[5]
[4:0] REFMON pin
Enable CLK
frequency
monitor
Enable REF2
(REFIN)
frequency
monitor
Enable REF1
(REFIN)
frequency
monitor
control
Description
[5] [4] [3]
1
1
1
1
1
1
Enables or disables the CLK frequency monitor.
[7] = 0; disable the CLK frequency monitor (default).
[7] = 1; enable the CLK frequency monitor.
Enables or disables the REF2 frequency monitor.
[6] = 0; disable the REF2 (REFIN) frequency monitor (default).
[6] = 1; enable the REF2 (REFIN) frequency monitor.
REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
[5] = 0; disable the REF1 (REFIN) frequency monitor (default).
[5] = 1; enable the REF1 (REFIN) frequency monitor.
Selects the signal that is connected to the REFMON pin.
[4]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
[2]
0
0
1
1
1
1
[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
[1]
1
1
0
0
1
1
Level or
Dynamic
Signal
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
Rev. 0 | Page 65 of 76
[0]
0
1
0
1
0
1
Level or
Dynamic
Signal
LVL
LVL
LVL
LVL
LVL
LVL
Signal at REFMON Pin
Ground, dc (default).
REF1 clock (differential reference when in differential mode).
REF2 clock (not applicable in differential mode).
Selected reference to PLL (differential reference when in differential
mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential mode);
active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of CLK).
Status of CLK frequency (active high).
Selected reference (low = REF1, high = REF2).
DLD; active low.
Holdover active (active high).
LD pin comparator output (active high).
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in differential mode).
Signal at LD Pin
(DLD) AND (Status of selected reference) AND (status of VCO).
Status of CLK frequency (active low).
Selected reference (low = REF2, high = REF1).
DLD; active low.
Holdover active (active low).
Not applicable, do not use.
AD9522-5