ADF4157BRUZ-RL Analog Devices Inc, ADF4157BRUZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADF4157BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4157BRUZ-RL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4157EB1Z - BOARD EVALUATION FOR ADF4157
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4157
FUNCTION REGISTER (R3) MAP
With R3[2:0] set to 011, the on-chip function register is
programmed as shown in Figure 20.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Σ-Δ Reset
For most applications, DB14 should be set to 0. When DB14 is
set to 0, the Σ-Δ modulator is reset on each write to Register 0.
If it is not required that the Σ-Δ modulator be reset on each
Register 0 write, this bit should be set to 1.
Lock Detect Precision (LDP)
When DB[7] is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
DB[6] sets the phase detector polarity. When the VCO
characteristics are positive, this should be set to 1. When they
are negative, it should be set to 0.
Phase Detector Polarity
DB31
0
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
RESERVED
0
0
0
0
0
Figure 20. Function Register (R3) Map
0
0
Rev. A | Page 16 of 24
0
U12
0
1
0
SD RESET
ENABLED
DISABLED
0
U12
RF Power-Down
DB[5] provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. While in software power-
down mode, the part retains all information in its registers.
Only when supplies are removed are the register contents lost.
When a power-down is activated, the following events occur:






RF Charge Pump Three-State
DB[4] puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
RF Counter Reset
DB[3] is the RF counter reset bit for the ADF4157. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
0
All active dc current paths are removed.
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF
The input shift register remains active and capable of
loading and latching data.
0
RESERVED
U11
0
1
0
IN
x input is debiased.
U10
0
LDP
24 PFD CYCLES
40 PFD CYCLES
0
1
0
PD POLARITY
NEGATIVE
POSITIVE
0
U11
U9
0
1
U10
POWER-DOWN
DISABLED
ENABLED
U9
U8
U8
0
1
U7
U7
0
1
CP
THREE-STATE
DISABLED
ENABLED
C3(0) C2(1) C1(1)
CONTROL
COUNTER
RESET
DISABLED
ENABLED
BITS