ADF4157BRUZ-RL Analog Devices Inc, ADF4157BRUZ-RL Datasheet - Page 20

• Manufacturer Part Number: ADF4157BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4157BRUZ-RL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4157EB1Z - BOARD EVALUATION FOR ADF4157
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4157
the input reference to avoid a possible feedthrough path on
the board.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however,
RF frequencies lower than this can be used, providing the mini-
mum slew rate specification of 400 V/μs is met. An appropriate
LVDS driver can be used to square up the RF signal before it is
fed back to the ADF4157 RF input. The FIN1001 from Fairchild
Semiconductor is one such LVDS driver.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit
download of the ADIsimPLL™ software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter architec-
tures are allowed.
OPERATING WITH WIDE LOOP FILTER
BANDWIDTHS
If a wide loop filter bandwidth is used (>60 kHz), fluctuations
in the phase noise profile may be noticed on channels that are
close to integer multiples of the PFD frequency. This is due to
operation of the charge pump close to the dead zone. To improve
the phase noise, a bleed current can be enabled to bias the charge
www.analog.com/pll
for a free
Rev. A | Page 20 of 24
pump away from the dead zone. To enable this, set Bit DB[24:23]
in Register 4. Using this mode has the added advantage of
improving the integer boundary spurs by 4 dB to 5 dB. Note
that it is also safe to use this mode if the loop filter bandwidth
is <60 kHz.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board (PCB) should be
at least as large as the exposed pad. On the printed circuit
board, there should be a clearance of at least 0.25 mm between
the thermal pad and the inner edges of the pad pattern. This
ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated into the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 ounce of copper to plug the
via. The user should connect the PCB thermal pad to AGND.