ADG2188YCPZ-HS-RL7 Analog Devices Inc, ADG2188YCPZ-HS-RL7 Datasheet - Page 8

IC,ANALOG SWITCH,SINGLE,8X8 CROSSPOINT,CMOS,LLCC,32PIN,PLASTIC

ADG2188YCPZ-HS-RL7

Manufacturer Part Number
ADG2188YCPZ-HS-RL7
Description
IC,ANALOG SWITCH,SINGLE,8X8 CROSSPOINT,CMOS,LLCC,32PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
I²Cr
Datasheet

Specifications of ADG2188YCPZ-HS-RL7

Function
Crosspoint Switch
Circuit
1 x 8:8
On-state Resistance
50 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
12V, 15V
Current - Supply
.05µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADG2188EBZ - BOARD EVAL FOR ADG2188
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADG2188YCPZ-HS-RL7TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADG2188YCPZ-HS-RL7
Manufacturer:
Maxim
Quantity:
101
ADG2188
Parameter
t
t
t
t
1
2
3
TIMING DIAGRAM
11
11A
12
SP
Guaranteed by initial characterization. All values measured with input filtering enabled. C
0.3 V
High speed I
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
DD
and 0.7 V
SDA
SCL
1
2
C is available only in -HS models
S = START CONDITION
P = STOP CONDITION
DD
Conditions
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
P
.
C
C
C
C
C
C
B
B
B
B
B
t
B
7
= 100 pF maximum
= 100 pF maximum
= 100 pF maximum
= 400 pF maximum
= 400 pF maximum
= 400 pF maximum
S
t
6
t
2
2
2
2
2
t
11
t
4
Min
20 + 0.1 C
10
20
20 + 0.1 C
10
20
20 + 0.1 C
10
20
0
0
ADG2188 Limit at T
Figure 2. Timing Diagram for 2-Wire Serial Interface
B
B
B
t
1
t
12
Max
1000
300
40
80
1000
300
80
160
300
300
40
80
50
10
t
Rev. 0 | Page 8 of 28
3
MIN
, T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
B
refers to capacitive load on the bus line; t
Description
t
t
t
Pulse width of suppressed spike
RCL
RCL1
FCL
S
and after an acknowledge bit
, fall time of SCL signal
, rise time of SCL signal
, rise time of SCL signal after a repeated start condition
t
5
t
10
t
6
R
and t
t
8
F
are measured between
P
t
9

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