ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 16

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

POWER DISSIPATION ADSP-21060L (3.3 V)
These specifications apply to the internal power portion of V
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
Parameter
I
I
I
I
NOTESS
1
2
3
ADSP-21060/ADSP-21060L
The test program used to measure I
I
Idle denotes ADSP-21060L state during execution of IDLE instruction.
DDINPEAK
DDINHIGH
DDINLOW
DDIDLE
power measurements made using typical applications are less than specified.
DDINHIGH
is a composite average based on a range of high activity code. I
%PEAK × I
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Idle)
DDINPEAK
DDINPEAK
Peak Activity (I
Multifunction
Cache
2 per Cycle (DM and PM)
1 per Cycle
+ %HIGH × I
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
3
1
2
2
DDINHIGH
DDINPEAK
+ %LOW × I
)
Test Conditions
t
t
t
t
t
t
V
CK
CK
CK
CK
CK
CK
DDINLOW
DD
DD
= 30 ns, V
= 25 ns, V
= 30 ns, V
= 25 ns, V
= 30 ns, V
= 25 ns, V
= max
only. See the Power Dissipation section of this data sheet for calcula-
is a composite average based on a range of low activity code.
High Activity (I
Multifunction
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
DDINLOW
DD
DD
DD
DD
DD
DD
= max
= max
= max
= max
= max
= max
+ %IDLE × I
DDINHIGH
)
DDIDLE
Max
540
600
425
475
250
275
180
= power consumption
Single Function
Low Activity (I
Internal Memory
None
1 per 2 Cycles
DDINLOW
Units
mA
mA
mA
mA
mA
mA
mA
)