ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 24

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-2106x bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
Parameter
Timing Requirements:
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
NOTES
1
2
3
ADSP-21060/ADSP-21060L
t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
t
SADRI
HADRI
SRWLI
HRWLI
RWHPI
SDATWH
HDATWH
SDDATO
DATTR
DACKAD
ACKTR
= 4 + DT/8.
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
SRWLI
DACKAD
(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
WRITE ACCESS
Address, SW Setup before CLKIN
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN
RD/WR Low Hold after CLKIN
RD/WR Pulse High
Data Setup before WR High
Data Hold after WR High
Data Delay after CLKIN
Data Disable after CLKIN
ACK Delay after Address, SW
ACK Disable after CLKIN
READ ACCESS
ADDRESS
CLKIN
DATA
(OUT)
DATA
ACK
WR
(IN)
SW
RD
2
3
3
1
t
SDDATO
Min
15 + DT/2
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
0 – DT/8
–1 – DT/8
ADSP-21060
t
DACKAD
t
SADRI
memory space). The bus master must meet these (bus slave)
timing requirements.
Max
5 + DT/2
8 + 7DT/16
19 + 5DT/16
7 – DT/8
9
6 – DT/8
ACKTR
t
t
SRWLI
SRWLI
.
t
HADRI
t
SDATWH
Min
15 + DT/2
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
0 – DT/8
–1 – DT/8
ADSP-21060L
t
t
t
HDATWH
HRWLI
HRWLI
t
t
DATTR
ACKTR
Max
5 + DT/2
8 + 7DT/16
19 + 5DT/16
7 – DT/8
9
6 – DT/8
t
t
RWHPI
RWHPI
SRWLI
(min)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns