ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 35

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Serial Ports
Parameter
External Clock
Timing Requirements:
t
t
t
t
t
t
Internal Clock
Timing Requirements:
t
t
t
t
External or Internal Clock
Switching Characteristics:
t
t
External Clock
Switching Characteristics:
t
t
t
t
Internal Clock
Switching Characteristics:
t
t
t
t
t
Enable and Three-State
Switching Characteristics:
t
t
t
t
t
t
Gated SCLK with External TFS
(Mesh Multiprocessing)
Timing Requirements:
t
t
External Late Frame Sync
Switching Characteristics:
t
t
To
and hold, 2) data delay & data setup and hold, and 3) SCLK width.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HODTE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
DDTEN
DDTTE
DDTIN
DDTTI
DCLK
DPTR
STFSCK
HTFSCK
DDTLFSE
DDTENFS
determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync se
TFS/RFS Setup before TCLK/RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup before TCLK
before RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
RFS Delay after RCLK (Internally
Generated RFS)
RFS Hold after RCLK (Internally
Generated RFS)
TFS Delay after TCLK (Internally
Generated TFS)
TFS Hold after TCLK (Internally
Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TFS Delay after TCLK (Internally
Generated TFS)
TFS Hold after TCLK (Internally
Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TCLK/RCLK Width
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN
SPORT Disable after CLKIN
TFS Setup before CLKIN
TFS Hold after CLKIN
Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 0
Data Enable from late FS or MCE = 1,
MFD = 0
5
1
4
3
3
3
3
3
3
1
; RFS Setup
1
1
3
3
1
1
3
3
3
3
3
3
1, 2
1, 2
1
5
Min
3.5
4
1.5
4
9.5
t
8
1
3
3
3
3
5
–1.5
0
(t
3.5
0
5
t
3
CK
CK
SCLK
/2
/2) – 2
ADSP-21060
Max
13
13
16
4.5
7.5
(t
10.5
3
22 + 3DT/8
17
12
SCLK
/2) + 2
ADSP-21060/ADSP-21060L
Min
3.5
4
1.5
4
9.0
t
8
1
3
3
3
3
5
–1.5
0
(t
4.0
0
5
t
3.5
CK
CK
SCLK
/2
/2) – 2.5
ADSP-21060L
Max
13
13
16
4.5
7.5
(t
10.5
3
22 + 3DT/8
17
12.8
SCLK
/2) + 2.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tup