ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of Wait states specified in WAIT register) × t
NOTES
1
2
3
ADSP-21060/ADSP-21060L
The falling edge of MSx, SW, BMS is referenced.
ACK Delay/Setup: User must meet t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
SSDATI
HSDATI
DAAK
SACKC
HACK
DADRO
HADRO
DPGC
DRDO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
of ACK (High).
Data Setup before CLKIN
Data Hold after CLKIN
ACK Delay after Address, MSx,
SW, BMS
ACK Setup before CLKIN
ACK Hold after CLKIN
Address, MSx, BMS, SW Delay
after CLKIN
Address, MSx, BMS, SW Hold
after CLKIN
PAGE Delay after CLKIN
RD High Delay after CLKIN
WR High Delay after CLKIN
RD/WR Low Delay after CLKIN
Data Delay after CLKIN
Data Disable after CLKIN
ADRCLK Delay after CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
1, 2
1
DAAK
or t
3
2
DSAK
or synchronous specification t
CK
Min
3 + DT/8
3.5 – DT/8
6.5 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
0 – DT/8
4 + DT/8
t
(t
(t
8 + DT/4
CK
.
CK
CK
/2) – 2
/2) – 2
ADSP-21060
SACKC
Max
14 + 7 DT/8 + W
7 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
for deassertion of ACK (Low), all three specifications must be met for assertion
Min
3 + DT/8
3.5 – DT/8
6.5 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
0 – DT/8
4 + DT/8
t
(t
(t
8 + DT/4
CK
CK
CK
/2) – 2
/2) – 2
ADSP-21060L
Max
14 + 7 DT/8 + W
7 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns