ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 27

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Memory Read—Bus Master on Page 25
Table 16. Synchronous Read/Write—Bus Master
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
The falling edge of MSx, SW, BMS is referenced.
ACK delay/setup: user must meet t
See
SSDATI
HSDATI
DAAK
SACKC
HACK
DADRO
HADRO
DPGC
DRDO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
(high).
Example System Hold Time Calculation on Page 47
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address, Selects
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, SW Delay After CLKIN
Address, MSx, BMS, SW Hold After CLKIN
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
ADRCLK Delay After CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
DAAK
or t
DSAK
and
or synchronous specification t
Memory Write—
for calculation of hold times given capacitive and dc loads.
2
3
Rev. F | Page 27 of 64 | March 2008
1, 2
SAKC
1
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
Bus Master on Page
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see
Read/Write—Bus Slave on Page
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Min
3 + DT/8
3.5 – DT/8
6.5+DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
(t
(t
4 + DT/8
t
CK
CK
CK
/2 – 2)
/2 – 2)
26). When accessing a slave ADSP-2106x,
5 V and 3.3 V
29). The slave ADSP-2106x
Max
14 + 7DT/8 + W
7 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
Synchronous
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns