ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 27
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ADUC7036BCPZ-RL
Manufacturer Part Number
ADUC7036BCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036BCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7036BCPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, the following
specific code sequence must be executed to initiate this
operation:
Set Bit 3 in FEExMOD.
Write 0xFFC3 in FEExADR.
Write 0x3CFF in FEExDAT.
Run the mass erase command (Code 0x06) in FEExCON.
This sequence is illustrated by the following example:
Int a = FEExSTA;
cleared
FEExMOD = 0x08
FEExADR = 0xFFC3
FEExDAT = 0x3CFF
FEExCON = 0x06;
while (FEExSTA & 0x04){} //Wait for command
to finish
It should be noted that to run the mass erase command via
FEE0CON, the write protection on the lower 64 kB must be
disabled. That is, FEE1HID/FEE1PRO are set to 0xFFFFFFFF.
This setting can be accomplished by first removing the protec-
tion or by erasing the lower 64 kB.
FEE0STA and FEE1STA Registers
Name: FEE0STA and FEE1STA
Address: 0xFFFF0E00 and 0xFFFF0E80
Default Value: 0x20
Access: Read only
Function: These 8-bit, read only registers can be read by user
code, and they reflect the current status of the Flash/EE
memory controllers.
// Ensure FEExSTA is
// Mass erase command
Rev. C | Page 27 of 132
Table 14. FEE0STA and FEE1STA MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
FEE0ADR and FEE1ADR Registers
Name: FEE0ADR and FEE1ADR
Address: 0xFFFF0E10 and 0xFFFF0E90
Default Value: 0x0000 (FEE1ADR). For FEE0ADR, see the
System Identification FEE0ADR section.
Access: Read/write access
Function: These 16-bit registers dictate the address acted upon
when a Flash/EE command is executed via FEExCON.
The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
Description
Not used. These bits are not used and always read as 0.
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEExMOD register is set.
Cleared automatically when the FEExSTA register is read
by user code.
Flash/EE controller busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
Command fail.
Set automatically when a command written to FEExCON
completes unsuccessfully.
Cleared automatically when the FEExSTA register is read
by user code.
Command successful.
Set automatically by the MCU when a command is
completed successfully.
Cleared automatically when the FEE0STA register is read
by user code.
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ADuC7036