ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 98
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ADUC7036BCPZ-RL
Manufacturer Part Number
ADUC7036BCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036BCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7036BCPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADuC7036
High Voltage Configuration0 Register
Name: HVCFG0
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR and does not
appear in the MMR memory map. It is accessed via the HVCON register interface. Data to be written to this register is loaded via the
HVDAT MMR, and data is read back from this register via the HVDAT MMR.
Table 74. HVCFG0 Bit Designations
Bit
7
6
5
4
3
2
1 to 0
Description
Wake-up/STI thermal shutdown disable.
Set to 1 to disable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
Cleared to 0 to enable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
Precision oscillator enable bit.
Set to 1 to enable the precision 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including a high
voltage interface latency of 10 μs).
Cleared to 0 to power down the precision 131 kHz oscillator.
Bit serial device (BSD) mode enable bit.
Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation.
Cleared to 0 to enable the internal (LIN) pull-up resistor on the LIN/BSD pin.
Wake-up (WU) assert bit.
Set to 1 to assert the external WU pin high.
Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
Power supply monitor (PSM) enable bit.
Set to 1 to enable the power supply (voltage at the VDD pin) monitor. If IRQ3 (IRQEN[16]) is enabled, the PSM
generates an interrupt if the voltage at the VDD pin drops below 6 V.
Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
Low voltage flag (LVF) enable bit.
Set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power-up to
determine if the REG_DVDD voltage previously dropped below 2.1 V.
Cleared to 0 to disable the LVF function.
LIN operating mode. These bits enable/disable the LIN driver.
00 = LIN disabled.
01 = reserved (not LIN V2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
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