ADUC7036CCPZ-RL Analog Devices Inc, ADUC7036CCPZ-RL Datasheet - Page 102
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADUC7036CCPZ-RL
Manufacturer Part Number
ADUC7036CCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036CCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-VFQFN Exposed Pad, CSP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 102 of 132
- Download datasheet (2Mb)
ADuC7036
WAKE-UP (WU) PIN
The wake-up (WU) pin is a high voltage GPIO controlled
through HVCON and HVDAT.
Wake-Up (WU) Pin Circuit Description
By default, the WU pin is configured as an output with an
internal 10 kΩ pull-down resistor and high-side FET driver.
In its default mode of operation, the WU pin is specified to
generate an active high system wake-up request by forcing the
external system WU bus high. User code can assert the WU
output by writing directly to HVCFG0[4].
Note that the output responds only after a 10 μs latency has elapsed;
this latency is inherent in a serial communication between the
HVCON or HVDAT MMR and the high voltage interface (see
the High Voltage Peripheral Control Interface section).
The internal FET is capable of sourcing significant current;
therefore, substantial on-chip self-heating may occur if this
driver is asserted for a long time period. For this reason,
a monoflop (that is, a 1.3 sec timeout timer) is included.
OUTPUT CONTROL
SHORT-CIRCUIT
PROTECTION
HVCFG0[4]
HVMON[0]
HVMON[7]
NORMAL
NORMAL
IMMUNITY
GLITCH
400µs
READBACK
HVCFG1[4]
ENABLE
SHORT-CIRCUIT
TRIP REFERENCE
~1V
Figure 42. WU Circuit, Block Diagram
Rev. C | Page 102 of 132
6.6kΩ
3.3kΩ
IO_VSS
R1
R2
VDD
INTERNAL
SENSE
RESISTOR
6kΩ
INTERNAL
10kΩ
RESISTOR
By default, the monoflop is enabled and disables the wake-up
driver after 1.3 sec. It is possible to disable the monoflop through
HVCFG1[1]. If the wake-up monoflop is disabled, the wake-up
driver should be disabled after 1.3 sec.
The WU pin also features a short-circuit detection feature. When
the wake-up pin sources more than 100 mA typically for 400 μs,
a high voltage interrupt is generated, and HVMON[0] is set.
A thermal shutdown event disables the WU driver. The WU
driver must be reenabled manually after using HVCFG1[3]
after a thermal event.
The WU pin can be configured in I/O mode by writing a 1 to
HVCFG1[4]. In this mode, a rising or falling edge immediately
generates a high voltage interrupt. HVMON[7] directly reflects
the state of the external WU pin and indicates if the external
wake-up bus (including R
39 Ω) is above or below a typical voltage of 3 V.
OPEN-CIRCUIT
DIAGNOSTIC
RESISTOR
HVCFG1[0]
EXTERNAL
WU PIN
CURRENT-LIMIT
EXTERNAL
RESISTOR
39Ω
LOAD
= 1 kΩ, C
C
91nF
LOAD
LOAD
R
1kΩ
= 91 nF, and R
LOAD
EXTERNAL
WAKE-UP
BUS
LIMIT
=
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