ADUC7036CCPZ-RL Analog Devices Inc, ADUC7036CCPZ-RL Datasheet - Page 48
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ADUC7036CCPZ-RL
Manufacturer Part Number
ADUC7036CCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036CCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-VFQFN Exposed Pad, CSP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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ADuC7036
Current Channel ADC Control Register
Name: ADC0CON
Address: 0xFFFF050C
Default Value: 0x0000
Access: Read/write
Function: This 16-bit register is used to configure the I-ADC.
Note that if the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset.
Table 37. ADC0CON MMR Bit Designations
Bit
15
14, 13
12 to 10
9
8
7, 6
5, 4
3 to 0
Description
Current channel ADC enable.
Set to 1 by user code to enable the I-ADC.
Cleared to 0 to power down the I-ADC and reset the respective ADC ready bit in the ADCSTA MMR to 0.
IIN current source enable.
00 = current sources off.
01 = enables the 50 μA current source on IIN+.
10 = enables the 50 μA current source on IIN−.
11 = enables the 50 μA current source on both IIN− and IIN+.
Not used. These bits are reserved for future functionality and should be written as 0.
Current channel ADC output coding.
Set to 1 by user code to configure I-ADC output coding as unipolar.
Cleared to 0 by user code to configure I-ADC output coding as twos complement.
Not used. This bit is reserved for future functionality and should be written as 0.
Current channel ADC input select.
00 = IIN+, IIN− are selected.
01 = IIN−, IIN− are selected. Diagnostic, internal short configuration.
10 = V
selected, REG_AVDD is used for VREF in this mode. This leads to ADC0DAT scaled by 2.
11 = not defined.
Current channel ADC reference select.
00 = internal, 1.2 V precision reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMDE[5].
01 = external reference inputs (VREF, GND_SW) selected.
10 = external reference inputs divided-by-2 (VREF, GND_SW)/2 selected, which allows an external reference up to REG_AVDD.
11 = (REG_AVDD, AGND) divided-by-2 selected.
Current channel ADC gain select. The nominal I-ADC full-scale input voltage = (VREF/gain).
0000 = I-ADC gain of 1.
0001 = I-ADC gain of 2.
0010 = I-ADC gain of 4.
0011 = I-ADC gain of 8.
0100 = I-ADC gain of 16.
0101 = I-ADC gain of 32.
0110 = I-ADC gain of 64.
0111 = I-ADC gain of 128.
1000 = I-ADC gain of 256.
1001 = I-ADC gain of 512.
1xxx = I-ADC gain is undefined.
REF
/136, 0 V, diagnostic, test voltage for gain settings ≤ 128. Note that if (REG_AVDD, AGND) divided-by-2 reference is
Rev. C | Page 48 of 132
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