CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 18

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

18
5.3.3
5.3.4
Manual Ratio Modifier (R-Mod)
The manual Ratio Modifier is used to internally multiply/divide the currently addressed R
stored in the register space remain unchanged). The available options for R
Table 2 on page
The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio
(R
its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio
modifier.
Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only
The Automatic R-Modifier uses the status of the CLK_IN Frequency Range Indicator (see
on page
Table
Like with R-Mod, the Ratio
ifier is enabled by the AutoRMod bit.
It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected
by the RModSel[2:0] bits and is used to calculate the Effective Ratio (see
Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A
converters. For example, if the clock applied to CLK_IN is the audio sample rate, Fs (also known as the
word, frame or Left/Right clock), and SysClk is 12.288 MHz (REF_CLK = 12.288 MHz with RefClkDiv[1:0]
Referenced Control
Ratio 0-3
RModSel[2:0]
EFF
),
3.
.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
see “Effective Ratio (REFF)” on page
14) to implement a frequency dependent multiply of the currently addressed R
........................“R-Mod Selection (RModSel[2:0])” section on page 28
18.
FsDetect[1:0]
RModSel[2:0]
Register Location
00
01
10
000
001
010
100
101
011
110
111
0-3
Table 3. Automatic Ratio Modifier
stored in the register space remain unchanged. The Automatic Ratio-Mod-
Table 2. Ratio Modifier
f
SysClk
96 - 224
19. If R-Mod is not desired, RModSel[2:0] should be left at
> 224
< 96
/ f
CLK_IN
Ratio Modifier
0.0625
0.125
0.25
0.5
1
2
4
8
Auto R Modifier
0.25
0.5
1
Section 5.3.5 on page
MOD
are summarized in
CS2000-CP
UD
UD
section 5.2.1
(the Ratio
as shown in
DS761PP1
19).
0-3