CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 37

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

DS692PP1
7. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high
rate and then downsample to the outgoing rate. Internal filtering is designed so that a full input audio bandwidth of
20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the
output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing
artifacts in the output signal. Any jitter in the incoming signal has little impact on the dynamic performance of the rate
converter and has no influence on the output clock.
7.1
7.1.1
7.1.2
7.2
SRC Data Resolution and Dither
When using the serial audio input port in left justified and I²S Modes, all input data is treated as 24-bits wide.
Any truncation that has been done prior to the CS8422 to less than 24-bits should have been done using
an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will
be truncated to the bit depth set through the
is set to 16 bits, and the input data is 24-bits wide, then truncation distortion will occur. Similarly, in any serial
audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks),
then the input words will be truncated, causing truncation distortion at low levels. In summary, there is no
dithering mechanism on the input side of the CS8422, and care must be taken to ensure that no truncation
occurs.
The output side of the SRC can be set to 16, 18, 20, or 24. Dithering is applied and is automatically scaled
to the selected output word length. This dither is not correlated between left and right channel.
SRC Locking
The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this in-
formation to set up various parameters inside the SRC block. The SRC takes some time to make this cal-
culation (approximately ~100 ms when Fso = 48 kHz).
The SRC_UNLOCK signal is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK
pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute its output.
The SRC_UNLOCK signal is available through the control port register 15h, or through the SRC_UNLOCK
pin in Hardware Mode.
Hardware Mode Control
In Hardware Mode, the SRC is the data source for SDOUT1, and its serial output port data resolution is
controlled through the SAOF pin. See
Software Mode Control
In Software Mode, the serial port data resolution is controlled through the
(0Bh)”,
SDOUT2 (0Dh)”
“Serial Audio Output Data Format - SDOUT1
registers.
Section 8.1 on page 40
“Serial Audio Input Data Format (0Bh)”
(0Ch)”, and
for more details.
“Serial Audio Output Data Format -
“Serial Audio Input Data Format
register. If the bit depth
CS8422
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