CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 66

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

66
12.3.2 Isolating Transformer Requirements
12.4
12.4.1 AES3 Channel Status (C) Bit Management
Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on
transformer selection
Channel Status Buffer Management
The CS8422 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels (5 x 2 x 8
= 80 bits). The user may read from this buffer’s RAM through the control port.
The buffering scheme involves two buffers, named D and E, as shown in
represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port
address 23h) is the consumer/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the first
five bytes of C data.
The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPO
pins in Software Mode. The C data is serially shifted out of the CS8422 clocked by the rising and falling
edges of OLRCK or VLRCK.
Figure 31. Receiver Input Attenuation – Single-ended Input
Figure 32. Receiver Input Attenuation – Differential Input
V
+
-
in
V
V
in-
in+
Twisted
75 Ω
Coax
110 Ω
(1)
(2)
Pair
R1
R1 = 75 – R2
R2 =
(1) R =
(2) R
R2
247.5
in
.01µF
V
= 55 - R
in
V
R
R
in+
726
in
in
- V
2
in-
RX
AGND
CS8422
R
RXN
RXP
CS8422
AGND
Figure
33. The MSB of each byte
CS8422
DS692PP1