CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 61

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

DS692PP1
11.22 Receiver Status (16h)
CS_UPDATE RCVR_RATE1 RCVR_RATE0
7
0
CS_UPDATE - Determines whether channel status registers and RCVR_RATE are updated in the presence
of
RCVR_RATE - Input sample rate represented in the channel status data of incoming AES3 data.
RX_LOCK - AES3 Receiver PLL Lock
BLK_VERR - Block Validity Error. Updated on DETC boundaries
BLK_CERR - Block Confidence Error. Updated on DETC boundaries
BLK_BERR - Block Biphase Error. Updated on DETC boundaries
BLK_PERR - Block Parity Error. Updated on DETC boundaries
0 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary.
1 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary if
no biphase, confidence, parity, or CRCC error has occurred during the reception of the channel status
block.
00 - Reserved
01 - 32 kHz
10 - 44.1 kHz
11 - 48 kHz
0 - The PLL has not achieved lock for more than 2 Z preambles or AES3 input is not driving PLL.
1 - Goes high 2 Z preambles after the PLL has achieved lock when an AES3 input has been selected to
drive the PLL.
0 - The Validity bit of the incoming AES3 data has remained low during the input of the last AES3 data
block.
1 - The Validity bit of incoming AES3 data has gone high at some point during the input of the last AES3
data block.
0 - The Confidence bit associated with incoming AES3 data has remained high during the input of the last
AES3 data block.
1 - The Confidence bit associated with incoming AES3 data has gone low at least once during the input
of the last AES3 data block.
0 - There has been no biphase error associated with incoming AES3 data during the input of the last AES3
data block.
1 - There has been at least one biphase error associated with incoming AES3 data during the input of the
last AES3 data block.
0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3
data block.
a receiver error (register 14h).
6
-
5
-
RX_LOCK
4
-
BLK_VERR
3
-
BLK_CERR
2
-
BLK_BERR
1
-
BLK_PERR
CS8422
0
-
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