CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 9

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CS8422-DNZR

Manufacturer Part Number
CS8422-DNZR
Description
IC 24-bit 192kHz SRC S/PDIF Receiver
Manufacturer
Cirrus Logic Inc
Datasheets
DS692PP1
1. PIN DESCRIPTION
1.1
Pin Name
RX[3:0],
RXP/RXN[1:0]
VA
AGND
AD0/CS
AD1/CDIN
SCL/CCLK
SDA/CDOUT
Software Mode
Pin #
10
1
2
5
6
3
4
7
8
9
RX1/RXN0
RX2/RXP1
RX3/RXN1
RX0/RXP0
Pin Description
AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF
encoded digital data. RX[3:0] comprise the single-ended input multiplexer. RXP[1:0] comprise the
non-inverting inputs of the differential input multiplexer and RXN[1:0] comprise the inverting inputs
of the differential input multiplexer. Unused inputs should be tied to AGND/DGND.
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure
that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter perfor-
mance of the recovered clock.
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Address Bit 0 (I²C) / Software Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8422 into SPI Control Port Mode. With no falling edge, the CS8422 defaults to I²C Mode. In I²C
Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on
the CS8422. See
Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin.
In SPI Mode, CDIN is the input data line to the control port interface. See
on page
Software Clock (Input) - Serial control interface clock used to clock control data bits into and out of
the CS8422.
Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O
data line. In SPI Mode, CDOUT is the output data from the control port interface on the CS8422.
AD1/CDIN
AD0/CS
AGND
VA
42.
1
3
5
2
4
6
7
8
“Control Port Description” on page
32
9
10
31
11
30
32-Pin QFN Package
Thermal Pad
Top-Down View
12
29
13
28
14
27
15
26
42.
25
16
24
23
22
21
20
19
18
17
VD_FILT
OSCLK2
SDOUT2
VL
DGND
V_REG
GPO2
GPO1
“Control Port Description”
CS8422
9

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