CY7C1470BV33-200AXC Cypress Semiconductor Corp, CY7C1470BV33-200AXC Datasheet
CY7C1470BV33-200AXC
Specifications of CY7C1470BV33-200AXC
Available stocks
Related parts for CY7C1470BV33-200AXC
CY7C1470BV33-200AXC Summary of contents
Page 1
... Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Cypress Semiconductor Corporation Document Number: 001-15032 Rev. *H CY7C1472BV25, CY7C1474BV25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2 × ...
Page 2
Logic Block Diagram – CY7C1470BV25 (2 M × 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Logic Block Diagram – CY7C1472BV25 ...
Page 3
Logic Block Diagram – CY7C1474BV25 (1 M × 72) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ...
Page 4
Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Burst Read Accesses .................................................. 8 Single Write Accesses ................................................. 8 Burst Write Accesses .................................................. 9 Sleep Mode ................................................................. 9 Linear Burst Address ...
Page 5
Pin Configurations DQPc 1 DQc 2 DQc DDQ DQc 6 DQc 7 DQc 8 DQc DDQ 11 DQc 12 DQc CY7C1470BV25 ...
Page 6
Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout NC/576M NC/1G A CE2 C DQP DDQ DDQ ...
Page 7
Pin Definitions Pin Name IO Type A0 Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the A1 Synchronous CLK Input- Byte Write Select Inputs, Active LOW. Qualified with WE ...
Page 8
Pin Definitions (continued) Pin Name IO Type TMS Test Mode Select TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock Clock Input to the JTAG Circuitry. V Power Supply ...
Page 9
Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQ /DQP for CY7C1470BV25, DQ a,b,c,d a,b,c,d CY7C1472BV25, DQ /DQP ...
Page 10
Truth Table The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Address Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) External Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) External Dummy Read (Continue Burst) Write Cycle (Begin Burst) ...
Page 11
Partial Write Cycle Description The partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Function (CY7C1470BV25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ...
Page 12
IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full ...
Page 13
Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12. During power up, ...
Page 14
CLK captured in the boundary scan register. After the data is captured possible to shift out the data by putting the TAP into the Shift-DR ...
Page 15
TAP AC Switching Characteristics [12, 13] Over the Operating Range Parameter Clock t TCK Clock Cycle Time TCYC t TCK Clock Frequency TF t TCK Clock HIGH time TH t TCK Clock LOW time TL Output Times t TCK Clock ...
Page 16
V TAP AC Test Conditions Input pulse levels................................................V Input rise and fall time .....................................................1 ns Input timing reference levels........................................ 1.25 V Output reference levels ............................................... 1.25 V Test load termination supply voltage ........................... 1.25 V TAP DC Electrical Characteristics ...
Page 17
Identification Codes Instruction Code EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the ...
Page 18
Boundary Scan Exit Order (4 M × 18) Bit # 165-ball ID Bit # ...
Page 19
Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65 °C to +150 °C Ambient Temperature with Power Applied .......................................... –55 °C to +125 °C Supply Voltage ...
Page 20
Electrical Characteristics (continued) [15, 16] Over the Operating Range (continued) Parameter Description I Automatic CE SB3 Power Down Current—CMOS Inputs I Automatic CE SB4 Power Down Current—TTL Inputs Capacitance Tested initially and after any design or process changes that may ...
Page 21
Switching Characteristics [18, 19] Over the Operating Range Parameter Description [20 (typical) to the First Access Read or Write Power CC Clock t Clock Cycle Time CYC F Maximum Operating Frequency MAX t Clock HIGH CH t Clock ...
Page 22
Switching Waveforms Figure 2 shows read-write timing waveform CYC CLK CENS CENH CH CEN t t CES CEH CE ADV/ ADDRESS Data In-Out (DQ) ...
Page 23
Switching Waveforms (continued) Figure 3 shows NOP, STALL and DESELECT Cycles waveform CLK CEN CE ADV/LD WE BWx A1 A2 ADDRESS Data In-Out (DQ) WRITE READ D(A1) Q(A2) Figure 4 shows ZZ Mode timing waveform. CLK ZZ t ...
Page 24
Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress ...
Page 25
Package Diagrams Figure 5. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Document Number: 001-15032 Rev. *H CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 51-85050 *D Page [+] Feedback ...
Page 26
Package Diagrams (continued) Figure 6. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 001-15032 Rev. *H CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 51-85165 *B Page [+] Feedback ...
Page 27
Document History Page Document Title: CY7C1470BV25/CY7C1472BV25/CY7C1474BV25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15032 REV. ECN No. Issue Date Orig. of Change ** 1032642 See ECN VKN/KKVTMP *A 1562503 ...
Page 28
... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-15032 Rev. *H NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. ...