CY7C1470BV33-200AXC Cypress Semiconductor Corp, CY7C1470BV33-200AXC Datasheet - Page 21

• Manufacturer Part Number: CY7C1470BV33-200AXC
• Description: CY7C1470BV33-200AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470BV33-200AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-15032 Rev. *H
18. Timing reference is 1.25 V when V
19. Test conditions shown in (a) of
20. This part has a voltage regulator internally; t
21. t
22. At any supplied voltage and temperature, t
23. This parameter is sampled and not 100% tested.
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
MAX
Parameter
steady-state voltage.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
CHZ
[20]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High Z
Clock to Low Z
OE HIGH to Output High Z
OE LOW to Output Low Z
Address Setup Before CLK Rise
Data Input Setup Before CLK Rise
CEN Setup Before CLK Rise
WE, BW
ADV/LD Setup Before CLK Rise
Chip Select Setup
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
CC
EOHZ
(typical) to the First Access Read or Write
are specified with AC test conditions shown in (b) of
x
x
[18, 19]
AC Test Loads and Waveforms on page 20
Setup Before CLK Rise
Hold After CLK Rise
DDQ
[21, 22, 23]
[21, 22, 23]
= 2.5 V.
Description
EOHZ
power
is less than t
is the time power is supplied above V
[21, 22, 23]
[21, 22, 23]
EOLZ
and t
CHZ
is less than t
unless otherwise noted.
AC Test Loads and Waveforms on page
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
0.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
1.4
0.4
DD
CLZ
1
–
–
–
–
–
0
250 MHz
minimum initially, before a read or write operation can be initiated.
to eliminate bus contention between SRAMs when sharing the same data
CY7C1472BV25, CY7C1474BV25
Max
250
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
200 MHz
Max
20. Transition is measured ±200 mV from
200
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1470BV25
Min
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
–
–
0
167 MHz
Max
167
3.4
3.4
3.4
3.4
Page 21 of 28
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–
–
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–
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–
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–
–
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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ns
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