CYWUSB6935-48LTXC Cypress Semiconductor Corp, CYWUSB6935-48LTXC Datasheet - Page 18
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CYWUSB6935-48LTXC
Manufacturer Part Number
CYWUSB6935-48LTXC
Description
CYWUSB6935-48LTXC
Manufacturer
Cypress Semiconductor Corp
Specifications of CYWUSB6935-48LTXC
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Length (mm)
7mm
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6935-48LTXC
Manufacturer:
ST
Quantity:
1 200
Table 20. Threshold Low
Table 21. Threshold High
Table 22. Wake Enable
Document Number : 38-16008 Rev. *G
Bit
7:1 Reserved
6:0 Threshold Low
Bit
Bit
6:0 Threshold High The Threshold High value is used to determine the number of matched chips allowed when attempting to
0
7
7
Reserved
Reserved
Wakeup
Enable
Reserved
Reserved
7
7
7
Name
Addr: 0x1A
Addr: 0x1C
Addr: 0x19
Name
Name
These bits are reserved and should be written with zeroes.
Wakeup interrupt enable.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communi-
cations.
This bit is reserved and should be written with zero.
The Threshold Low value is used to determine the number of missed chips allowed when attempting to
correlate a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would
result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting
the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the
value of the received data bit. This value along with the Threshold High value determine the correlator count
values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to inter-
ference and the dependability of the received data. By allowing a minimal number of erroneous chips the
dependability of the received data increases while the robustness to interference decreases. On the other
hand increasing the maximum number of missed chips means reduced data integrity but increased
robustness to interference and increased range.
6
6
6
This bit is reserved and should be written with zero.
correlate a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit
PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was
received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be
erroneous while still identifying the value of the received data bit. This value along with the Threshold Low
value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine
the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal
number of erroneous chips the dependability of the received data increases while the robustness to inter-
ference decreases. On the other hand increasing the maximum number of missed chips means reduced data
integrity but increased robustness to interference and increased range.
5
5
5
Reserved
REG_THRESHOLD_H
REG_THRESHOLD_L
4
4
4
REG_WAKE_EN
Threshold High
Threshold Low
Description
Description
Description
3
3
3
2
2
2
1
1
1
CYWUSB6935
Default: 0x08
Default: 0x38
Default: 0x00
Page 18 of 36
Wakeup
Enable
0
0
0
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