CYWUSB6935-48LTXC Cypress Semiconductor Corp, CYWUSB6935-48LTXC Datasheet - Page 29
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CYWUSB6935-48LTXC
Manufacturer Part Number
CYWUSB6935-48LTXC
Description
CYWUSB6935-48LTXC
Manufacturer
Cypress Semiconductor Corp
Specifications of CYWUSB6935-48LTXC
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Length (mm)
7mm
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6935-48LTXC
Manufacturer:
ST
Quantity:
1 200
Power Management Timing
Table 40. Power Management Timing
Notes
Document Number : 38-16008 Rev. *G
t
t
t
t
t
t
t
t
t
t
t
23. The PD pin must be asserted at power up to ensure proper crystal startup.
24. When X13OUT is enabled.
25. Both the polarity and the drive method of the IRQ pin are programmable. See page 11 for more details.
26. A wakeup event is triggered when the PD pin is deasserted.
27. Measured with CTS ATXN6077A crystal.
PDN_X13
SPI_RDY
PWR_RST
RST
PWR_PD
WAKE
PD
SLEEP
WAKE_INT
STABLE
STABLE2
Parameter
(Reg 0x05, bits 1:0).
(Reg 0x1C, bit 0=1).
X 1 3 O U T
X13OUT
R E S E T
V C C
P D
IRQ
PD
Time from PD deassert to X13OUT
Time from oscillator stable to start of SPI transactions
Power on to RESET deasserted
Minimum RESET asserted pulse width
Power on to PD deasserted
PD deassert to clocks running
Minimum PD asserted pulse width
PD assert to low power mode
PD deassert to IRQ
PD deassert to clock stable
IRQ assert (wake interrupt) to clock stable
t
t
P W R _ R S T
P W R _ P D
t
SLEEP
[25]
Description
t
assert (wake interrupt)
t
P D N _ X 1 3
PD
(The values below are dependent upon oscillator network component selection)
[23]
Figure 14. Power On Reset/Reset Timing
[24]
Figure 15. Sleep / Wake Timing
Figure 15
t
S P I_ R D Y
t
WAKE
t
WAKE_INT
illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable register
[26]
to within ±10 ppm
to within ±10 ppm
Conditions
V
CC
at 2.7V
t
STABLE
Figure 15
t
STABLE2
illustrates default values for the Configuration register
1300
1300
Min
10
–
1
1
–
–
–
–
–
t
R S T
2000
2100
2100
2000
2000
Typ
50
–
–
–
–
–
[27]
CYWUSB6935
Max
–
–
–
–
–
–
–
–
–
–
–
Page 29 of 36
Unit
µs
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
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