DSPIC33FJ128GP204T-I/ML Microchip Technology, DSPIC33FJ128GP204T-I/ML Datasheet - Page 399
![16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128GP204T-I/ML
Manufacturer Part Number
DSPIC33FJ128GP204T-I/ML
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128GP204T-I/MLTR
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Revision D (November 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE A-3:
© 2011 Microchip Technology Inc.
“High-Performance, 16-Bit Digital Signal
Controllers”
Section 11.0 “I/O Ports”
Section 18.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 21.0 “10-Bit/12-Bit Analog-to-
Digital Converter (ADC)”
Section 22.0 “Audio Digital-to-Analog
Converter (DAC)”
Section 27.0 “Special Features”
Section 30.0 “Electrical Characteristics”
Section 31.0 “High Temperature Electrical
Characteristics”
“Product Identification System”
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
Section Name
MAJOR SECTION UPDATES
Added information on high temperature operation (see “Operating
Range:”).
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Updated the two baud rate range features to: 10 Mbps to 38 bps at
40 MIPS.
Updated the ADC block diagrams (see Figure 21-1 and Figure 21-2).
Removed last sentence of the first paragraph in the section.
Added a shaded note to Section 22.2 “DAC Module Operation”.
Updated Figure 22-2: “Audio DAC Output for Ramp Input
(Unsigned)”.
Updated the second paragraph and removed the fourth paragraph in
Section 27.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 27-1).
Updated the Absolute Maximum Ratings for high temperature and
added Note 4.
Removed parameters DI26, DI28, and DI29 from the I/O Pin Input
Specifications (see Table 30-9).
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 30-12).
Removed Table 30-43: Audio DAC Module Specifications. Original
contents were updated and combined with Table 30-42 of the same
name.
Added new chapter with high temperature specifications.
Added the “H” definition for high temperature.
Update Description
DS70292E-page 399
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