DSPIC33FJ16GP304-E/PT Microchip Technology, DSPIC33FJ16GP304-E/PT Datasheet
DSPIC33FJ16GP304-E/PT
Specifications of DSPIC33FJ16GP304-E/PT
Available stocks
Related parts for DSPIC33FJ16GP304-E/PT
DSPIC33FJ16GP304-E/PT Summary of contents
Page 1
... Microchip Technology Inc. dsPIC33FJ16GP304 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70290G ...
Page 2
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Flash program memory ( Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • ...
Page 4
... Communication Modules: • 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes 2 • I C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration ...
Page 5
... Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONTROLLER FAMILIES Device dsPIC33FJ32GP202 28 32 dsPIC33FJ32GP204 44 32 dsPIC33FJ16GP304 44 16 Note 1: Only two out of three timers are remappable ...
Page 6
... Pin Diagrams 28-Pin SDIP, SOIC, SSOP AN0/V REF AN1/V REF PGED1/AN2/C2IN-/RP0 PGEC1/AN3/C2IN+/RP1 AN4/RP2 AN5/RP3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4 SOSCO/T1CK/CN0/RA4 PGED3/ASDA1/RP5 (2) 28-Pin QFN-S (1) PGED1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/AN3/C2IN+/RP1 /CN5/RB1 (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See ...
Page 7
... Pin Diagrams (Continued) (2) 44-Pin QFN (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/RP18 /CN10/RC2 V V OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally. © ...
Page 8
... Pin Diagrams (Continued) 44-Pin TQFP (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/RP18 /CN10/RC2 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See DS70290G-page 8 11 AN11/RP13 AN12/RP12 25 9 PGEC2/RP11 26 8 PGED2/RP10 ...
Page 9
... Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 31 5.0 Flash Program Memory.............................................................................................................................................................. 57 6.0 Resets ....................................................................................................................................................................................... 63 7.0 Interrupt Controller ..................................................................................................................................................................... 71 8.0 Oscillator Configuration .............................................................................................................................................................. 99 9.0 Power-Saving Features............................................................................................................................................................ 109 10.0 I/O Ports ................................................................................................................................................................................... 113 11 ...
Page 10
... NOTES: DS70290G-page 10 © 2011 Microchip Technology Inc. ...
Page 11
... DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices not intended comprehensive refer- ence source. To complement the infor- mation in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www ...
Page 12
... FIGURE 1-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
Page 13
... TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Type Type AN0-AN12 I Analog No CLKI I ST/CMOS No CLKO O — No OSC1 I ST/CMOS No OSC2 I/O — No SOSCI I ST/CMOS No SOSCO O — No CN0-CN30 IC1-IC2 I ST Yes IC7-IC8 Yes OCFA I ST Yes OC1-OC2 O — ...
Page 14
... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Type Type PGED1 I PGEC1 PGED2 I PGEC2 PGED3 I PGEC3 — No CAP V P — Analog No REF Analog No REF VDD MCLR I Avss — Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; ...
Page 15
... Basic Connection Requirements Getting started with the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
Page 16
... FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 10 µ Tantalulm R R1 MCLR C dsPIC33F 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source ...
Page 17
... ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to ...
Page 18
... Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first ...
Page 19
... CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 20
... Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt ...
Page 21
... FIGURE 3-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP AccA Accumulators AccB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 ...
Page 22
... CPU Control Registers CPU control registers include: • Register 3-1: “SR: CPU Status Register” • Register 3-2: “CORCON: CORE Control Register” REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (2) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> ...
Page 23
... REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 8 DC: MCU ALU Half Carry/Borrow bit carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized ...
Page 24
... REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...
Page 25
... Arithmetic Logic Unit (ALU) The dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...
Page 26
... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70290G-page 26 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
Page 27
... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
Page 28
... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...
Page 29
... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
Page 30
... NOTES: DS70290G-page 30 © 2011 Microchip Technology Inc. ...
Page 31
... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DEVICES dsPIC33FJ32GP202/204 GOTO Instruction Reset Address ...
Page 32
... Program Memory ‘Phantom’ Byte (read as ‘0’) DS70290G-page 32 4.1.2 INTERRUPT AND TRAP VECTORS All dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices reserve the addresses between 0x00000 and organized in 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
Page 33
... Data Address Space The dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
Page 34
... FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DEVICES WITH 2 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 0x0001 2 Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70290G-page 34 ...
Page 35
... X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...
Page 36
TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
Page 37
... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
Page 38
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 ...
Page 39
TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
Page 40
TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
Page 41
TABLE 4-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
Page 42
... TABLE 4-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
Page 43
... TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC ...
Page 44
TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
Page 45
... LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-19: PORTC REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 — — ...
Page 46
TABLE 4-20: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
Page 47
... In addition to its use as a working register, the W15 register in the dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown ...
Page 48
... TABLE 4-23: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS ...
Page 49
... Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...
Page 50
... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers ...
Page 51
... FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-24: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right ...
Page 52
... Interfacing Program and Data Memory Spaces The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
Page 53
... FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
Page 54
... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...
Page 55
... READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDH) ...
Page 56
... NOTES: DS70290G-page 56 © 2011 Microchip Technology Inc. ...
Page 57
... Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V ...
Page 58
... RTSP Operation The dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time ...
Page 59
... REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE — bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
Page 60
... REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 61
... PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Programmers can program one row of program Flash memory at a time this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
Page 62
... EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...
Page 63
... RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 64
... REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
Page 65
... REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-on Reset has occurred Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset ...
Page 66
... System Reset The dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
Page 67
... FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR Reset 2 BOR Reset SYSRST Oscillator Clock FSCM Device Status Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the V ...
Page 68
... TABLE 6-2: OSCILLATOR DELAY Symbol V POR threshold POR T POR extension time POR V BOR threshold BOR T BOR extension time BOR T Programmable power-up time delay PWRT T Fail-Safe Clock Monitor Delay FSCM Note: When the device exits condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc ...
Page 69
... FIGURE 6-3: BROWN-OUT SITUATIONS V DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset ...
Page 70
... Configuration Mismatch Reset To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs. ...
Page 71
... Reset process. The to the dsPIC33FJ16GP304 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user application can use a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine ...
Page 72
... FIGURE 7-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...
Page 73
... TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address Number Number 8 0 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C ...
Page 74
... TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 ...
Page 75
... Interrupt Control and Status Registers dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices implement a total of 17 registers for the interrupt controller: • Interrupt Control Register 1 (INTCON1) • Interrupt Control Register 2 (INTCON2) • Interrupt Flag Status Registers (IFSx) • Interrupt Enable Control Registers (IECx) • ...
Page 76
... REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
Page 77
... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
Page 78
... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...
Page 79
... REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
Page 80
... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 81
... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © ...
Page 82
... REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 83
... REGISTER 7-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
Page 84
... REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 85
... REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. ...
Page 86
... REGISTER 7-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 87
... REGISTER 7-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
Page 88
... REGISTER 7-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 89
... REGISTER 7-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 90
... REGISTER 7-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 91
... REGISTER 7-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...
Page 92
... REGISTER 7-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 93
... REGISTER 7-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...
Page 94
... REGISTER 7-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP< ...
Page 95
... REGISTER 7-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP< ...
Page 96
... REGISTER 7-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...
Page 97
... Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 98
... NOTES: DS70290G-page 98 © 2011 Microchip Technology Inc. ...
Page 99
... Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. FIGURE 8-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 ( OSC2 POSCMD< ...
Page 100
... CPU Clocking System The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 device provides seven system clock options: • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT EC) Oscillator • Primary Oscillator with PLL • Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator • ...
Page 101
... PLL” being the selected oscillator mode. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0.8-8 MHz. FIGURE 8-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. TABLE 8-1: ...
Page 102
... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 103
... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator ...
Page 104
... REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 105
... REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. ...
Page 106
... REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • ...
Page 107
... REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 108
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different ...
Page 109
... POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power Savings Modes” (DS70196) of the “ ...
Page 110
... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9 ...
Page 111
... REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — T3MD bit 15 R/W-0 U-0 R/W-0 I2C1MD — U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 112
... REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 113
... I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) of the “dsPIC33F/PIC24H Reference Manual”, which is available ...
Page 114
... Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ16GP304 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 115
... Peripheral Pin Select A major challenge in general-purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low-pin count devices application where more than one peripheral must be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option ...
Page 116
... TABLE 10-1: REMAPPABLE PERIPHERAL INPUTS Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI1 Data Input SPI1 Clock Input ...
Page 117
... TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> NULL U1TX U1RTS SDO1 SCK1OUT SS1OUT OC1 OC2 10.6.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes ...
Page 118
... Peripheral Pin Select Registers The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices implement 17 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (9) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK See Section 10.6.3.1 “Control Register Lock” ...
Page 119
... REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 120
... REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 121
... REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 122
... REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 123
... REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 124
... REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 125
... REGISTER 10-8: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 126
... REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 127
... REGISTER 10-10: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 128
... REGISTER 10-12: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 129
... REGISTER 10-14: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 130
... REGISTER 10-16: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 131
... REGISTER 10-18: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 132
... REGISTER 10-20: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 133
... REGISTER 10-22: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 134
... NOTES: DS70290G-page 134 © 2011 Microchip Technology Inc. ...
Page 135
... TIMER1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 136
... REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 ...
Page 137
... TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 138
... FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 139
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70290G-page 139 ...
Page 140
... REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2/3 ...
Page 141
... REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timer3 On bit 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘ ...
Page 142
... NOTES: DS70290G-page 142 © 2011 Microchip Technology Inc. ...
Page 143
... INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) of the “dsPIC33F/PIC24H Reference Manual”, which is available ...
Page 144
... Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 145
... OUTPUT COMPARE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output (DS70209) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 146
... Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 147
... Output Compare Register REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 148
... NOTES: DS70290G-page 148 © 2011 Microchip Technology Inc. ...
Page 149
... SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Interface (SPI)” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 150
... REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 151
... REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (2) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 152
... REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) ...
Page 153
... REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 154
... NOTES: DS70290G-page 154 © 2011 Microchip Technology Inc. ...
Page 155
... INTER-INTEGRATED 2 CIRCUIT™ (I C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit™ C™)” (DS70195) of the “dsPIC33F/ PIC24H Family Reference Manual” ...
Page 156
... FIGURE 16-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70290G-page 156 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 157
... REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
Page 158
... REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 159
... REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 160
... REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 161
... REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 162
... NOTES: DS70290G-page 162 © 2011 Microchip Technology Inc. ...
Page 163
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 device family. The UART is a full-duplex asynchronous system communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and ® ...
Page 164
... REGISTER 17-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Hardware Clearable R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 165
... REGISTER 17-1: UxMODE: UART bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits ...
Page 166
... REGISTER 17-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 167
... REGISTER 17-2: U STA: UART x bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only Receiver is Idle ...
Page 168
... NOTES: DS70290G-page 168 © 2011 Microchip Technology Inc. ...
Page 169
... ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 170
... FIGURE 18-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16GP304 AND dsPIC33FJ32GP204 DEVICES AN0 AN12 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 ...
Page 171
... FIGURE 18-2: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP202 DEVICES AN0 AN12 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN9 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN10 V REFL CH123NA CH123NB ...
Page 172
... FIGURE 18-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (2) RC Clock T CY OSC ( Note 1: Refer to Figure 8-2 for the derivation the clock frequency See the ADC Electrical Characteristics for the exact RC clock value. DS70290G-page 172 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier ...
Page 173
... REGISTER 18-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend Cleared by hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating ...
Page 174
... REGISTER 18-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘ ...
Page 175
... REGISTER 18-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG<2:0> bit 15 R-0 U-0 R/W-0 BUFS — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ A 000 ...
Page 176
... REGISTER 18-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 U-0 U-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock ...
Page 177
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 178
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 179
... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 ...
Page 180
... REGISTER 18-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 181
... REGISTER 18-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 182
... NOTES: DS70290G-page 182 © 2011 Microchip Technology Inc. ...
Page 183
... SPECIAL FEATURES Note: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 devices not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to the “dsPIC33F/PIC24H Family Manual”. Please see the Microchip web site (www.microchip.com) for the latest ...
Page 184
... TABLE 19-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONFIGURATION BITS DESCRIPTION RTSP Bit Field Register Effect BWRP FBS Immediate Boot Segment Program Flash Write Protection BSS<2:0> FBS Immediate dsPIC33FJ32GP202 and dsPIC33FJ32GP204 Devices Only BSS<2:0> FBS Immediate dsPIC33FJ16GP304 Devices Only GSS<1:0> FGS ...
Page 185
... TABLE 19-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Bit Field Register Effect FCKSM<1:0> FOSC Immediate Clock Switching Mode bits IOL1WAY FOSC Immediate Peripheral Pin Select Configuration OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) POSCMD< ...
Page 186
... On-Chip Voltage Regulator All of the dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the ...
Page 187
... Watchdog Timer (WDT) For dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 19.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
Page 188
... JTAG Interface dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. 19.6 Code Protection and CodeGuard™ Security The dsPIC33FJ32GP202/204 ...
Page 189
... In-Circuit Serial Programming dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family digital signal controllers can be serially pro- grammed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence ...
Page 190
... NOTES: DS70290G-page 190 © 2011 Microchip Technology Inc. ...
Page 191
... INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 dsPIC33FJ16GP304 devices not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to the “dsPIC33F/PIC24H Family Manual”. Please see the Microchip web site (www.microchip.com) for the latest ...
Page 192
... Most instructions are a single double-word instructions are designed to provide all of the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles ...
Page 193
... TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Multiplicand and Multiplier working register pair for Square instructions ∈ Wm*Wm {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Multiplicand and Multiplier working register pair for DSP instructions ∈ Wm*Wn {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} One of 16 working registers ∈ ...
Page 194
... TABLE 20-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND ...
Page 195
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 10 BTSC BTSC f,#bit4 BTSC Ws,#bit4 11 BTSS BTSS f,#bit4 BTSS Ws,#bit4 12 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb 13 BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS ...
Page 196
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd ...
Page 197
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB 51 MUL MUL.SS Wb,Ws,Wnd MUL.SU Wb,Ws,Wnd MUL.US Wb,Ws,Wnd MUL.UU Wb,Ws,Wnd MUL.SU Wb,#lit5,Wnd MUL.UU Wb,#lit5,Wnd MUL ...
Page 198
... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 ...
Page 199
... DEVELOPMENT SUPPORT ® The PIC microcontrollers and dsPIC controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment ® - MPLAB IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families ...
Page 200
... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...