DSPIC33FJ16GP304-E/PT Microchip Technology, DSPIC33FJ16GP304-E/PT Datasheet - Page 47

• Manufacturer Part Number: DSPIC33FJ16GP304-E/PT
• Description: 16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GP304-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.6
In addition to its use as a working register, the W15
register
dsPIC33FJ16GP304 devices is also used as a
software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It pre-decrements for stack
pops and post-increments for stack pushes, as shown
in
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
When an EA is generated using W15 as a source or
destination pointer, the resulting address is compared
with the value in SPLIM. If the contents of the Stack
Pointer (W15) and the SPLIM register are equal and a
push operation is performed, a stack error trap will not
occur. The stack error trap will occur on a subsequent
push operation. For example, to cause a stack error
trap when the stack grows beyond address 0x1000 in
RAM, initialize the SPLIM with the value 0x0FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
© 2011 Microchip Technology Inc.
0x0000
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
Note:
Figure
15
000000000
4-4. For a PC push during any CALL
in
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
<Free Word>
the
PC<15:0>
PC<22:16>
dsPIC33FJ32GP202/204
CALL STACK FRAME
0
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
and
4.2.7
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for Boot Segment) is accessible only from the
Boot Segment Flash code when enabled. SSRAM
(Secure RAM segment for RAM) is accessible only
from the Secure Segment Flash code when enabled.
See
SSRAM SFRs.
4.3
The addressing modes shown in
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where:
Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal.
The result location can be either a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
Table 4-1
Instruction Addressing Modes
DATA RAM PROTECTION FEATURE
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing
Individual
different subsets of these addressing
modes.
for an overview of the BSRAM and
instructions
modes
Table 4-23
DS70290G-page 47
given
can
form the
support
above.