DSPIC33FJ16GP304-E/PT Microchip Technology, DSPIC33FJ16GP304-E/PT Datasheet - Page 100

• Manufacturer Part Number: DSPIC33FJ16GP304-E/PT
• Description: 16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GP304-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
8.1
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
device provides seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
8.1.1
8.1.1.1
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> bits (CLKDIV<10:8>).
8.1.1.2
The primary oscillator can use one of the following as
its clock source:
• XT (Crystal): Crystals and ceramic resonators in
• HS (High-Speed Crystal): Crystals in the range of
• EC (External Clock): The external clock signal is
8.1.1.3
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
8.1.1.4
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
8.1.1.5
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output
configuration is described in
Configuration”.
The FRC frequency depends on the FRC accuracy
(see
Tuning register (see
DS70290G-page 100
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
directly applied to the OSC1 pin.
Table
frequencies
CPU Clocking System
22-18) and the value of the FRC Oscillator
SYSTEM CLOCK SOURCES
Fast RC
Primary
Secondary
Low-Power RC
FRC
Register
for
device
8-4).
Section 8.1.3 “PLL
operation.
PLL
8.1.2
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 19.1 “Configuration Bits”
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
Oscillator
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The Configuration bits allow users to choose among 12
different clock modes, shown in
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) F
generate the device instruction clock (F
peripheral clock time base (F
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJ32GP202/204
and dsPIC33FJ16GP304 architecture.
Instruction execution speed or device operating
frequency, F
EQUATION 8-1:
8.1.3
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in
The output of the primary oscillator or FRC, denoted as
‘F
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
IN
OSC
’, is divided down by a prescale factor (N1) of 2, 3,
) is in the range of 12.5 MHz to 80 MHz, which
factor
SYSTEM CLOCK SELECTION
PLL CONFIGURATION
CY
Mode
, is given by:
‘N1’
F
CY
DEVICE OPERATING
FREQUENCY
Figure
Select
© 2011 Microchip Technology Inc.
=
is
F
-------------
OSC
8-2.
2
selected
Table
P
Configuration
OSC
). F
for further details.)
is divided by 2 to
8-1.
CY
CY
defines the
using
) and the
bits,
the