DSPIC33FJ16GS502-E/SP Microchip Technology, DSPIC33FJ16GS502-E/SP Datasheet - Page 113

• Manufacturer Part Number: DSPIC33FJ16GS502-E/SP
• Description: 16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-E/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 7-12:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices.
R/W-0
T2IE
U-0
—
2: These bits are unimplemented in dsPIC33FJ06GS202 devices.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Unimplemented: Read as ‘0’
ADIE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE
R/W-0
U-0
—
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
(1,2)
W = Writable bit
‘1’ = Bit is set
IC2IE
R/W-0
R/W-0
ADIE
(1,2)
U1TXIE
R/W-0
(1,2)
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U1RXIE
R/W-0
R/W-0
T1IE
(1,2)
(1,2)
SPI1IE
OC1IE
R/W-0
R/W-0
x = Bit is unknown
SPI1EIE
IC1IE
R/W-0
R/W-0
(1)
DS70318D-page 111
T3IE
INT0IE
R/W-0
R/W-0
(1,2)
bit 8
bit 0