DSPIC33FJ16GS502-E/SP Microchip Technology, DSPIC33FJ16GS502-E/SP Datasheet - Page 193

• Manufacturer Part Number: DSPIC33FJ16GS502-E/SP
• Description: 16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-E/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The
dsPIC33FJ16GSX02/X04 devices support up to two
input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 13-1:
© 2009 Microchip Technology Inc.
Note:
ICx Pin
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
INPUT CAPTURE
This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 12. “Input
Capture” (DS70198), which is available
on
(www.microchip.com).
dsPIC33FJ06GS101/X02
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
Prescaler
(1, 4, 16)
Counter
the
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
ICM<2:0> (ICxCON<2:0>)
Microchip
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Edge Detection Logic
Clock Synchronizer
families
web
ICxI<1:0>
and
site
and
Preliminary
of
(in IFSx Register)
Set Flag ICxIF
Interrupt
Logic
• Simple Capture Event modes:
• Capture timer value on every edge (rising and
• Prescaler Capture Event modes:
Each input capture channel can select one of the
two 16-bit timers (Timer2 or Timer3) for the time
base. The selected timer can use either an internal
or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
falling)
- Capture timer value on every 4th rising edge
- Capture timer value on every 16th rising
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
input at ICx pin
input at ICx pin
of input at ICx pin
edge of input at ICx pin
4 buffer locations are filled
FIFO
Logic
R/W
From 16-Bit Timers
TMR2 TMR3
1
ICxBUF
16
0
DS70318D-page 191
16
ICTMR
(ICxCON<7>)