DSPIC33FJ16MC304-E/PT Microchip Technology, DSPIC33FJ16MC304-E/PT Datasheet - Page 49

16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY

DSPIC33FJ16MC304-E/PT

Manufacturer Part Number
DSPIC33FJ16MC304-E/PT
Description
16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16MC304-E/PTTR
DSPIC33FJ16MC304-E/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip
Quantity:
175
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 4-26:
4.3.3
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing
instructions, move and accumulator instructions also
support
Addressing mode, also referred to as Register Indexed
mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
© 2011 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset
(Register Indexed)
Register Indirect with Literal Offset
Note:
Note:
Addressing Mode
Register
MOVE AND ACCUMULATOR
INSTRUCTIONS
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
modes
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Indirect
supported
with
by
Register
Wn is pre-modified (incremented or decremented) by a signed constant value
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA).
The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
to form the EA.
The sum of Wn and Wb forms the EA.
The sum of Wn and a literal forms the EA.
most
Offset
MCU
4.3.4
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.3.5
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Note:
Description
MAC INSTRUCTIONS
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
OTHER INSTRUCTIONS
DS70283H-page 49

Related parts for DSPIC33FJ16MC304-E/PT