AK4127VFP-E2 AKM Semiconductor Inc, AK4127VFP-E2 Datasheet - Page 13

• Manufacturer Part Number: AK4127VFP-E2
• Description: 6CH 192KHZ / 24-BIT ASYNCHRONOUS
• Manufacturer: AKM Semiconductor Inc
• Type: Sample Rate Converterr

Specifications of AK4127VFP-E2

• Applications: Automotive Systems, Home Theater, TV
• Mounting Type: Surface Mount
• Package / Case: 30-TSSOP (0.220", 5.60mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5857219

■
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 3 of
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”. When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the
TDM mode at the output port.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Note 10. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 11. The IBCIK must be continuous except when the clocks are changed.
Note 12. IBCIK = 32fsi is supported only 16bit LSB justified and I
Note 13. Fixed to DVSS.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
MS0593-E-02
Mode
Mode IDIF2
10
11
12
13
14
15
System Clock & Audio Interface Format for Input PORT
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
IMCLK = DVSS
ILRCK = Output
IBICK = Output
IMCLK = Input
ILRCK = Input
IBICK = Input
Master / Slave
H
H
H
H
L
L
L
L
Master
Slave
Table
IDIF1
H
H
H
H
L
L
L
L
2) or IBICK (Mode 4 ∼ 7 of
IDIF0
H
H
H
H
L
L
L
L
PLL2
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Table 1. Input Audio Interface Format (Input PORT)
24/16bit, I
24/20bit, MSB justified
24bit, I
24bit, MSB justified
16bit, LSB justified
20bit, LSB justified
24bit, LSB justified
PLL1
Table 2. PLL Setting (Input PORT)
SDTI Format
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
OPERATION OVERVIEW
2
S Compatible
2
S Compatible
Table
PLL0
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
2) in slave mode. The MCLK is not needed in slave mode. And
- 13 -
ILRCK Freq
16k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 108kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 108kHz
8k ∼ 216kHz
8k ∼ 96kHz
8k ∼ 54kHz
8k ∼ 54kHz
Table
(
(
ILRCK
Note 10
Note 11
Output
Input
2
S Compatible.
2) in master mode. The PLL2-0 pins and IDIF2-0
Reserved
)
)
IBICK
Output
Input
IBICK Freq
on IDIF2-0
Depending
(Note
(Note
128fsi
32fsi
64fsi
64fsi
64fsi
≥ 48fsi or 32fsi
11)
12)
IBICK Freq
≥ 32fsi
≥ 40fsi
≥ 48fsi
≥ 48fsi
64fs
64fs
(Note
(Note
IMCLK
needed.
needed.
128fsi
256fsi
512fsi
128fsi
192fsi
384fsi
768fsi
192fsi
Not
Not
13)
13)
Master / Slave
Master
Slave
(Note
Semi-Auto
Semi-Auto
Semi-Auto
Semi-Auto
SMUTE
Manual
Manual
Manual
Manual
Manual
[AK4127]
2010/05
14)