CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 10

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Figure 6.
all, there is a multiplexer which selects either the imager core
signal or an external pin EXTIN as the input of the amplifier.
EXTIN can be used for evaluation, or to feed alternative data to
the output.
SEL_EXTIN controls this switch.
Then, the signal is fed to the first amplifier stage. This stage has
an adjustable gain, controlled by a 4-bit word ('gc_bit0...3').
Then, the upper level of the signal must be clipped in some situa-
tions (clipping sometimes is necessary when the imager signal
is highly saturated, which affects the calibration level. This is
visible as black banding at the right side of bright objects in the
scene). In order to do this, a voltage should be applied to the
'Clip' pin. The signal is clipped if it is higher than Vclip - Vth,pmos,
where Vth,pmos is the PMOS threshold voltage and is typically
-1 V. If clipping is not necessary, 5 V should be applied to 'Clip'.
After this, the offset level is added. This offset level is set by a
DAC, controlled by a 4-bit word (DAC_bit0...3). The offset level
can be calibrated in two modes: fast offset adjustment or slow
offset adjustment. This is controlled by 'calib_s' and 'calib_f'. The
slow adjustment yields a somewhat cleaner image.
After this, the signal is buffered by a unity feedback amplifier and
it leaves the chip. This 2nd amplifier stage determines the
maximal readout speed, i.e., the bandwidth and the slew rate of
the output signal. The whole amplifier chain is designed for a
data rate of 10 Mpix/s (at 40 pF). (It is up to the experimenter to
increase this speed by reducing the various setting resistors)
Document Number: 38-05707 Rev. *C
shows the architecture of the output amplifier. First of
pixel array
sel_extin
extin
offset [0..3]
Vhigh_dac
Vlow_dac
Figure 6. Output Amplifier Architecture
gain [0..3]
unity gain
A
D
A
C
Table 4.
with a short functional description. Power and ground lines are
shared between the output amplifier and the image sensor.
Output Amplifier Offset Level Adjustment
The purpose of this adjustment is to bring the pixel voltage range
as good as possible within the ADC range. The offset level of the
output signal is controlled by a 4-bit resistive DAC. This DAC
selects the offset level on a linear scale between 2 reference
voltages. These reference voltages are applied to Vlow_dac and
Vhigh_dac.
This offset level is adjusted during the calibration phase. During
this phase, the amplifier input should be constant and refers to
the 'zero' signal situation. The IBIS4-1300 outputs a dark
reference signal after a row has been read out completely. This
signal can be used as the 'zero signal' reference. Alternatively
one can apply an external reference on pin EXTIN, which is
applied to the output amplifier when SEL_EXTIN is 1.
Offset adjustment can be done during row or frame blanking
time.
1.1.1.1.1
Clip
shows the IBIS4-1300 pins used by the output amplifier
+
1
Calib_f
Calib_s
CYII4SM1300AA
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