CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 12

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Table 4. Pins Involved in Output Amplifier Circuitry
Document Number: 38-05707 Rev. *C
Name
Analog Signals
Extin
Output
Digital Controls
Sel_extin
gc_bit0
gc_bit1
gc_bit2
gc_bit3
unitygain
calib_s
calib_f
dac_b0
dac_b1
dac_b2
dac_b3
Reference Voltages
Vlow_dac
Vhigh_dac
Nbias_oamp
Clip
No.
12
13
9
17
18
19
20
21
16
22
26
25
24
23
14
15
27
83
1 = external input pin (extin) is applied at the input of the amplifier
Function
External input of the output amplifier
Active if Sel_extin = 1
Analog output signal
To be connected to the input of the ADC (in_adc, pin 73)
0 = output amplifier is connected to the image sensor array
LSB
Control bits for output amplifier gain setting
Gain adjustment between 1.2 (0000) & 16X (1111)
MSB
1 = output amplifier in unity feedback mode
0 = output amplifier gain controlled by gc_bit0...3
Slow (or incremental) output offset level adjustment (calibration of output amplifier). Offset
adjustment converges after about 100 pulses on calib_s
Amplifier input should refer to a 'zero signal' at the moment of the 1->0 transition on calib_s
0 = connect to capacitor (of stage 2) and in- (of stage 1)
1 = connect to DAC output (of stage 2) and out (of stage1)
Fast (=in 1 cycle) output offset level adjustment (calibration of output amplifier)
Offset level is adjusted when both calib_f and unitygain are high
Amplifier input should refer to 'zero signal' when calib_f is high
1 = connect DAC output to offset of capacitor
0 = DAC output disconnected
LSB
Control bits for output offset level adjustment
Between Vlow_dac (0000) & Vhigh_dac (1111)
MSB
Low and high references for offset control DAC of the analog output.
The range of this resistive division DAC should be about 1V to 2.5V. If the range is not OK,
one will notice that it is not possible to adjust the output voltage to the appropriate level of
the ADC. As the internal division resistor is about 1.3 Kohm, we suggest to tie Vlow_dac
with 1K to GND and Vhigh_dac with 2K7 to VDD.
Output amplifier speed/power.
Connect with 100 K to VDD and decouple with 100 nF to GND. This setting yields 10 MHz
nominal pixel rate. Lowering the resistance does increasing this rate.
Voltage that can be used to clip the output signal
Clips output if output signal > 'Vclip - Vth, PMOS' with Vth,PMOS=-1V
Default: 5 V (no clipping)
CYII4SM1300AA
Page 12 of 35
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