CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 28

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Pin Configuration
Pin List
Document Number: 38-05707 Rev. *C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
No.
Nbiasarray
pbias2
Pbias
xmux_nbias
Sync_yr\
clk_yr
Eos_yr\
Eos_x\
Selextin
Gnd
Vdd
Extin
Output
Vlow_dac
Vhigh_dac
Calib_s
gc_bit0
gc_bit1
gc_bit2
gc_bit3
Unitygain
Calib_f
Dac_b3
Dac_b2
Dac_b1
Dac_b0
Nbias_oamp
Sync_x\
W
A
D
Signal Type Symbols
Name
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
D
W
W
W
W
D
D
W
W
W
W
A
D
Type
Word bit
Analog
Digital
I
I
I
I
I
I
O
O
I
G
P
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
1MEG to VDD and decouple to GND
1MEG to GND and decouple to VDD
1MEG to GND and decouple to VDD
100K to VDD and decouple to GND
low active (0=sync)
Shifts on falling edge
Active low
Active low
input selector for output amplifier
Analog GND
Analog VDD
external input to output amplifier
analog output of imager core
low reference voltage offset DAC
high reference voltage offset DAC
Slow dark offset level adjustment
Lsb
Msb
sets output amplifier in unity gain
fast dark offset level calibration
Msb
Lsb
100K to VDD and decouple to GND
low active (0=sync)
Description
O
G
P
I
I/O Symbols
Pixel source follower bias current
Column amp 1st source follower (after SHY)
bias current
Column amp current source bias current
X-multiplexing bias current (/6)
0 = reset right shift register
clock right shift register
low 1st clk_yr pulse after last row
low 1st clk_x pulse after last active column
1 = external input; [0] = imager core
+ 5 V DC
Connect to in_adc (p73)
+/- 1 V
+/- 2.5 V
0: connect to cap (st2) and in- (st1)
1: connect to rdac (st2) and output (st1)
gain control output amplifier
High active
High active
dac control for black offset level
dac control for black offset level
dac control for black offset level
dac control for black offset level
output amplifier bias current
0 = reset X shift register
Power supply
Ground
Output
Input
CYII4SM1300AA
Signal
Page 28 of 35
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