LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 17

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
external MOSFET off. To handle this situation, the TIMER
discharges C
SENSE voltage is less than 50mV. Therefore any intermit-
tent overload with V
of more than 2.5% will eventually trip the circuit breaker
and shut down the LTC4253A-ADJ. Figure 3 shows the
circuit breaker response time in seconds normalized to
1µF. The asymmetric charging and discharging of C
fair gauge of MOSFET heating.
The normalized circuit response time is estimated by:
POWER GOOD SEQUENCING
After the initial TIMER cycle, GATE ramps up to turn on the
external MOSFET which in turn pulls DRAIN low. When
GATE is within 2.8V of V
the power good sequence starts off a 5µA pull-up on the
SQTIMER pin which ramps up until it reaches the 4V
threshold then pulls low. When the SQTIMER pin floats,
this delay t
capacitor C
PWRGD1 asserts low after one t
up on another delay cycle. PWRGD2 asserts when EN2
goes high and PWRGD1 has asserted for more than one
C
t
SQT
T
(
t
µ
F
=
)
0.01
0.1
Figure 3. Circuit Breaker Response Time
4
10
SQ
=
SQT
1
V C
T
5
0
[
from SQTIMER to V
•
(
µ
slowly with a 5µA pull-down whenever the
205 8
is about 300µs. Connecting an external
A
SQ
20
U
+
FAULT DUTY CYCLE, D (%)
OUT
C
T
(µF)
t
•
IN
< 5V and an aggregate duty cycle
I
40
4
=
DRN
and DRAIN is lower than V
U
(205 + 8 • I
)
60
•
SQT
D
EE
4
DRN
−
W
I
modifies the delay to:
and SQTIMER ramps
5
DRN
) • D – 5
80
]
= 0µA
for D
4253A F03
100
>
2 5
U
. %
DRNL
T
is a
(5)
(6)
,
t
ramps up on another delay cycle. PWRGD3 asserts when
EN2 and EN3 go high and PWRGD2 has asserted for more
than one t
All three PWRGD signals are reset in UVLO, in UV condi-
tion, if RESET is high or when C
addition, PWRGD2 is reset by EN2 going low. PWRGD3 is
reset by EN2 or EN3 going low. An overvoltage condition
has no effect on the PWRGD flags. A 50µA current pulls
each PWRGD pin high when reset. As power modules
signal common are different from PWRGD, optoisolation
is recommended. These three pins can sink an optodiode
current. Figure 17 shows an NPN configuration for the
PWRGD interface. A limiting base resistor should be used
for each NPN and the module enable input should have
protection from negative bias current. Figure 17 also
shows how the LTC4253A-ADJ can be used to sequence
four power modules.
SOFT-START
Soft-start is effective in limiting the inrush current during
GATE start-up. From the Block Diagram, the internal SS
circuit consists of a current I
resistive divider. The resistive divider (47.5k/2.5k) scales
V
threshold:
After the initial timing cycle, SS ramps up from 0V to 1.4V
(28µA • 50k), ramping V
ACL amplifier will then limit the inrush current to V
R
ciently discharged and the ACL amplifier is in current limit
mode before GATE start-up.
There are two modes of SS ramp up. If SEL is set high and
the SS pin floats, an internal current source ramps SS from
0V to 1.4V in about 200µs. Connecting an external capaci-
tor, C
mate an RC response of:
SQT
SS
S
. The offset voltage, V
V
V
. When PWRGD2 successfully pulls low, SQTIMER
(t) down by 20 times to give the analog current limit
SS
ACL
SS
( )
, from SS to ground modifies the ramp to approxi-
t
( )
t
≈
SQT
=
V
SS
.
V
SS
20
⎛
⎜
⎜
⎝
1
( )
t
−
–
e
R C
V
SS SS
OS
ACL
OS
–
LTC4253A-ADJ
t
(t) from –10mV to 60mV. The
(10mV) ensures C
⎞
⎟
⎟
⎠
SS
T
(28µA) feeding into a
charges up to 4V. In
SS
is suffi-
17
ACL
4253a-adjf
(t)/
(7)
(8)