LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 24

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253A-ADJ
point A, setting off the second SQTIMER ramp-up. PWRGD2
pulls low at time point D when EN2 is high and PWRGD1
is low for more than one t
point E when EN2 and EN3 is high and PWRGD2 is low for
more than one t
mum voltage as determined by V
24
(–48RTN) – (–48V)
GND – V
SQT
SQTIMER
PWRGD1
PWRGD2
PWRGD3
SENSE
TIMER
DRAIN
EE
GATE
V
. At time point B, GATE reaches its maxi-
UVL
OVL
EN2
EN3
OUT
V
OR
UV
OV
SS
U
IN
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to V
1
SQT
U
V
GATEL
V
. PWRGD3 pulls low at time
LKO
UV CLEARS V
2
IN
V
V
UVHI
OVHI
.
W
UVHI
INITIAL TIMING
, CHECK OV < V
5µA
50µA
U
20 • (V
20 • (V
ACL
V
OVHI
CB
TMRH
20 • V
+ V
+ V
, RESET < 0.8V, GATE < V
V
TMRL
OS
OS
OS
)
)
50µA
3 4 5 6
TIMER CLEARS V
Undervoltage Timing
In Figure 10 when the UVL pin drops below V
point 1), the LTC4253A-ADJ shuts down with TIMER, SS
and GATE pulled low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears V
initial time cycle begins followed by a start-up cycle.
200µA + 8 • I
START-UP
GATE
7
50µA
V
89
SQTMRH
5µA
DRN
GATEL
A B
TMRL
V
V
V
V
V
, SENSE < V
, CHECK GATE < V
IN
ACL
CB
DRNCL
DRNL
– V
C
GATEH
5µA
5µA
CB
, SS < 20 • V
D
GATEL
, SENSE < V
E
OS
V
SQTMRL
5µA
AND TIMER < V
4253A F09
EE
UVHI
)
CB
AND SS < 20 • V
(time point 2), an
TMRL
OS
UVLO
4253a-adjf
(time