LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 22

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253A-ADJ
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
22
(–48RTN) – (–48V)
GND – V
SQTIMER
PWRGD1
PWRGD2
PWRGD3
SENSE
TIMER
DRAIN
EE
GATE
V
UVL
OVL
EN2
EN3
OUT
V
OR
UV
OV
SS
IN
U
1 2
V
IN
U
Figure 8. System Power-Up Timing (All Waveforms are Referenced to V
V
V
V
V
CLEARS V
UVHI
OVLO
LKO
GATEL
LKO
W
, CHECK UV > V
INITIAL TIMING
5µA
50µA
20 • (V
20 • (V
UVHI
U
ACL
, OVL < V
V
CB
TMRH
20 • V
+ V
+ V
V
TMRL
OS
OS
OS
OVLO
)
)
50µA
3 4 56
TIMER CLEARS V
, RESET < 0.8V, GATE < V
200µA + 8 • I
START-UP
time point 1, the supply ramps up, together with UV/OV,
V
slower rate as set by the V
point 2, V
UV > V
SENSE < V
GATE
OUT
7 89
50µA
V
SQTMRH
and DRAIN. V
5µA
A B
DRN
UVHI
TMRL
V
V
V
V
V
IN
IN
ACL
CB
DRNCL
DRNL
, CHECK GATE < V
CB
, OVL < V
– V
exceeds V
C
GATEL
, SS < 20 • V
GATEH
5µA
, SENSE < V
5µA
D
IN
OVLO
LKO
and the PWRGD signals follow at a
GATEL
V
IH
CB
, RESET < 0.8V, GATE < V
, SS < 20 • V
and the internal logic checks for
, SENSE < V
E
OS
V
SQTMRL
5µA
IN
EE
, and TIMER < V
V
4253A F08
IH
)
bypass capacitor. At time
CB
OS
AND SS < 20 • V
AND TIMER < V
TMRL
TMRL
OS
. When
4253a-adjf
GATEL
,