LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 29

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
to decline below V
and GATE releases at time point 8. At time point 9, SENSE
voltage falls below V
A third Soft-Start mode is shown in Figure 15c. The SEL
pin is tied low and a soft-start capacitor, C
to the SS pin. The behavior is similar to Figure 15b until
time point 4 when GATE is released and starts to ramp up.
Instead of continuing its ramp-up as in mode two, the SS
TIMER
SENSE
DRAIN
GATE
SS
20 • (V
V
END OF INITIAL TIMING CYCLE
12 3 4 5 6 7
GS(th)
(15a) Without External C
ACL
V
TMRH
V
+ V
TMRL
50µA
20 • V
OS
)
OS
20 • (V
200µA + 8 • I
7a
CB
ACL
+ V
U
PWRGD1
OS
CB
DRN
TIMER
SENSE
DRAIN
(t). The current limit loop shuts off
)
GATE
200µA + 8 • I
V
OUT
SS
and TIMER deactivates.
V
8 9
TMRH
U
(14a) Analog Current Limit Fault
Figure 14. Current Limit Behavior (All Waveforms are Referenced to V
1 2
V
V
V
50µA
SS
DRN
ACL
CB
DRNCL
10
Figure 15. Soft-Start Timing (All Waveforms are Referenced to V
V
5µA
DRNL
34
11
V
IN
– V
V
V
W
ACL
CB
GATEH
SS
SENSE
TIMER
DRAIN
GATE
5µA
, is connected
SS
END OF INITIAL TIMING CYCLE
12 3 4 56
V
GS(th)
U
V
(15b) With External C
TMRH
V
TMRL
20 • V
50µA
OS
200µA + 8 • I
20 • (V
ACL
7
+ V
PWRGD1
pin voltage is servoed at a voltage that is just above 0.2V
(20 • V
GATE ramping up freely. At time point 5, GATE ramps past
the external MOSFET’s threshold and inrush current starts
to flow. At time point 6, V
servo on SS is released while the GATE voltage is con-
trolled by the current limit amplifier with V
up from near zero. The result is a current profile (as
DRN
200µA + 8 • I
SENSE
TIMER
DRAIN
OS
GATE
V
OUT
)
20 • (V
V
V
8 9
DRNCL
TMRH
CB
SS
OS
DRN
50µA
V
V
V
1
+ V
10
ACL
CB
DRNCL
(14b) Fast Current Limit Fault
V
5µA
) to keep the current limit amplifier off and the
OS
V
DRNL
FCL
)
11
V
CB TIMES-OUT
2
IN
– V
V
ACL
GATEH
V
CB
TIMER
SENSE
DRAIN
GATE
SS
(15c) With SEL = Low and External C
SENSE
END OF INITIAL TIMING CYCLE
12 3 4 56
EE
V
GS(th)
LTC4253A-ADJ
)
EE
V
TMRH
V
)
TMRL
20 • V
goes above V
50µA
4253A F14
OS
200µA + 8 • I
20 • (V
ACL
+ V
7
DRN
OS
ACL
)
20 • (V
ACL
8 9
(t) ramping
CB
(t) and the
V
V
V
50µA
+ V
10
ACL
CB
DRNCL
V
29
5µA
OS
DRNL
4253a-adjf
)
11
V
IN
4253A F15
– V
SS
GATEH