LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 18

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253A-ADJ
When V
current limit mode and releases its pull-down on GATE. V
(t) = 20 • (V
> 20 • V
up and SS continues to ramp up. When GATE clears the
threshold of the external FET and inrush current starts flow-
ing, V
from zero. V
before going into analog current limit (Figure 4a).
If SEL is set low during SS ramp-up, V
it exceeds 20 • V
V
keep the ACL amplifier off and GATE ramping up freely. Once
GATE clears the threshold of the external FET, inrush cur-
rent starts flowing and V
will engage the ACL amplifier and mask off V
V
LTC4253A-ADJ enters analog current limit with V
(V
resultant inrush current profile presents a smooth ramp up
from zero (Figure 4b). If there is little inrush current so the
LTC4253A-ADJ does not enter current limit, V
be masked off when DRAIN goes below 2.39V (V
latched off when GATE goes within 2.8V of V
A minimum C
V
SS is discharged low during UVLO, UV, OV, during the
initial timing cycle, a latched circuit breaker fault or the
RESET pin going high.
18
SS
SS
SS
SS
is servoed at a voltage that is just above 20 • V
servo loop.
continues its RC ramp-up. In this way, the
(t)/20 – V
SENSE
ACL
50mV
GATE
V
OS
10V
50V
OUT
SS
1V
ACL
(t) = (V
= 0.2V (since V
OS
SENSE
(t) exceeds V
SS
+ V
OS
SS
of 5nF is required for the stability of the
OS
SENSE
will show an initial jump to clear this offset
) ramping up from close to zero. The
(t)/20 – V
U
= 0.2V and GATE starts its ramp-up.
(4a) SEL Set High
) from Equation 7. So when V
SENSE
SENSE
1ms/DIV
U
SENSE
OS
will jump above V
= 0V), GATE starts to ramp
) will have a positive offset
, the ACL amplifier exits
W
SS
is servoed when
4253A F04a
Figure 4. Two Modes of SS Ramp Up
SS
IN
SS
ACL
U
DRNL
(V
servo will
servo so
ACL
(t). This
GATEH
SS
OS
) and
(t) =
(t)
SS
to
).
GATE
GATE is pulled low to V
conditions: in UVLO, when RESET pulls high, in an
undervoltage condition, in an overvoltage condition, dur-
ing the initial timing cycle or a latched circuit breaker fault.
When GATE turns on, a 50µA current source charges the
MOSFET gate and any associated external capacitance.
V
Gate-drain capacitance (C
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
capacitor C
for the analog current limit loop.
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing; the GATE
high comparator looks for < 2.8V relative to V
together with DRAIN low comparator, starts power good
sequencing during GATE start-up.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to V
IN
limits the gate drive to no more than 14.5V.
SENSE
50mV
GATE
V
10V
OUT
50V
SS
1V
C
is adequate. C
GD
(4b) SEL Set Low
. Instead, a smaller value (≥10nF)
1ms/DIV
EE
C
GD
also provides compensation
under any of the following
) feedthrough at the first
4253A F04b
EE
IN
. When
4253a-adjf
and,
IN
,