P0059 Terasic Technologies Inc, P0059 Datasheet - Page 57

• Manufacturer Part Number: P0059
• Description: DE2-115 EVAL BOARD
• Manufacturer: Terasic Technologies Inc
• Series: Cyclone® IVr
• Type: FPGAr

Specifications of P0059

• Contents: Board, Cables, CD, DVD, Power Adapter, Remote Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: EP4CE115

4
The DE2-115 board provides Ethernet support via two Marvell 88E1111 Ethernet PHY chips. The
88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support
GMII/MII/RGMII/TBI MAC interfaces.
Figure 4-27
Here only RGMII and MII modes are supported on the board (The factory default mode is RGMII).
There is one jumper for each chip for switching work modes from RGMII to MII (See
Signal Name
PS2_CLK
PS2_DAT
PS2_CLK2
PS2_DAT2
4
Configuration
PHYADDR[4:0]
ENA_PAUSE
ANEG[3:0]
ENA_XC
DIS_125
HWCFG[3:0]
DIS_FC
DIS_SLEEP
SEL_TWSI
INT_POL
75/50OHM
.
.
1
1
4
4
G
G
i
i
g
g
shows the connection setup between the Gigabit Ethernet PHY (ENET0) and FPGA.
a
a
FPGA Pin No.
PIN_G6
PIN_H5
PIN_G5
PIN_F5
b
b
Description
PHY Address in MDIO/MDC Mode 10000 for Enet0;10001 for Enet1
Enable Pause
Auto negotiation configuration
for copper modes
Enable Crossover
Disable 125MHz clock
Hardware Configuration Mode
Disable fiber/copper interface
Energy detect
Interface select
Interrupt polarity
Termination resistance
i
i
t
t
Table 4-20 Default Configuration for Gigabit Ethernet
E
E
Figure 4-26 Y-Cable use for both Keyboard and Mouse
t
t
h
h
e
e
r
r
n
n
Table 4-19 PS/2 Pin Assignments
Description
PS/2 Clock
PS/2 Data
PS/2 Clock (reserved for second PS/2 device)
PS/2 Data (reserved for second PS/2 device)
e
e
t
t
T
T
r
r
Table 4-20
a
a
n
n
s
s
c
c
56
e
e
Default Value
1-Default Register 4.11:10 to 11
1110-Auto-neg, advertise all capabilities, prefer
master
0-Disable
1-Disable 125CLK
1011/1111 RGMII to copper/GMII to copper
1-Disable
1-Disable energy detect
0-Select MDC/MDIO interface
1-INTn signal is active LOW
0-50 ohm termination for fiber
i
i
v
v
describes the default settings for both chips.
e
e
r
r
I/O Standard
3.3V
3.3V
3.3V
3.3V
Figure
4-28).