P0059 Terasic Technologies Inc, P0059 Datasheet - Page 61

• Manufacturer Part Number: P0059
• Description: DE2-115 EVAL BOARD
• Manufacturer: Terasic Technologies Inc
• Series: Cyclone® IVr
• Type: FPGAr

Specifications of P0059

• Contents: Board, Cables, CD, DVD, Power Adapter, Remote Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: EP4CE115

to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore
audio and video chip won’t function correctly.
4
Although the DE2-115 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed
triple ADCs) can be used to implement a professional-quality TV encoder with the digital
processing part implemented in the Cyclone IV E FPGA.
TV encoder implemented in this manner.
Signal Name
TD_ DATA [0]
TD_ DATA [1]
TD_ DATA [2]
TD_ DATA [3]
TD_ DATA [4]
TD_ DATA [5]
TD_ DATA [6]
TD_ DATA [7]
TD_HS
TD_VS
TD_CLK27
TD_RESET_N
I2C_SCLK
I2C_SDAT
4
.
.
1
1
6
6
Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back
I
I
m
m
Figure 4-30 A TV Encoder that uses the Cyclone IV E FPGA and the ADV7123
p
p
l
l
e
e
m
m
FPGA Pin No.
PIN_E8
PIN_A7
PIN_D8
PIN_C7
PIN_D7
PIN_D6
PIN_E7
PIN_F7
PIN_E5
PIN_E4
PIN_B14
PIN_G7
PIN_B7
PIN_A8
e
e
n
n
t
t
i
i
n
n
Table 4-24 TV Decoder Pin Assignments
g
g
a
a
T
T
V
Description
TV Decoder Data[0]
TV Decoder Data[1]
TV Decoder Data[2]
TV Decoder Data[3]
TV Decoder Data[4]
TV Decoder Data[5]
TV Decoder Data[6]
TV Decoder Data[7]
TV Decoder H_SYNC
TV Decoder V_SYNC
TV Decoder Clock Input.
TV Decoder Reset
I2C Clock
I2C Data
V
E
E
n
n
c
c
60
o
o
d
d
e
e
r
r
Figure 4-30
shows a block diagram of a
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V