Si5351B-A-GU Silicon Laboratories Inc, Si5351B-A-GU Datasheet - Page 25

• Manufacturer Part Number: Si5351B-A-GU
• Description: Clock Generators & Support Products AnyRate 2 PLL 125MHz Clk w/VCXO&I2C 8out
• Manufacturer: Silicon Laboratories Inc
• Type: Any Frequency CMOS Clock Generatorr

Specifications of Si5351B-A-GU

• Mounting Style: SMD/SMT
• Max Input Freq: 0.008 MHz
• Max Output Freq: 133 MHz
• Number Of Outputs: 8
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Package / Case: QSOP-24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. Register Descriptions
Reset value = 0000 0000
Register 0. Device Status
Name
3:2
1:0
Bit
Type
7
6
5
4
Bit
REVID[1:0] Revision ID. Device revision number. Set at the factory.
SYS_INIT System Initialization Status.
Reserved Leave as default.
LOL_B
LOL_A
Name
SYS_INIT
LOS
D7
R
During power up the device copies the content of the NVM into RAM and performs a system
initialization. The device is not operational until initialization is complete. It is not recom-
mended to read or write registers in RAM through the I
plete. An interrupt will be triggered (INTR pin = 0, Si5351C only) during the system
initialization period.
0: System initialization is complete. Device is ready.
1: Device is in system initialization mode.
PLLB Loss Of Lock Status.
Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from CLKIN
or XTAL. A loss of lock will occur if the frequency of the reference clock forces the PLL to
operate outside of its lock range as specified in Table 3, or if the reference clock fails to meet
the minimum requirements of a valid input signal as specified in Table 4. An interrupt will be
triggered (INTR pin = 0, Si5351C) during a LOL condition.
0: PLL B is locked.
1: PLL B is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
PLL A Loss Of Lock Status.
PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL. A loss
of lock will occur if the frequency of the reference clock forces the PLL to operate outside of
its lock range as specified in Table 3, or if the reference clock fails to meet the minimum
requirements of a valid input signal as specified in Table 4. An interrupt will be triggered
(INTR pin = 0, Si5351C only) during a LOL condition.
0: PLL A is operating normally.
1: PLL A is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
CLKIN Loss Of Signal (Si5351C Only).
A loss of signal status indicates if the reference clock fails to meet the minimum requirements
of a valid input signal as specified in Table 4. An interrupt will be triggered (INTR pin = 0,
Si5351C only) during a LOS condition.
0: Valid clock signal at the CLKIN pin.
1: Loss of signal detected at the CLKIN pin.
LOL_B
D6
R
LOL_A
D5
R
Preliminary Rev. 0.95
LOS
D4
R
Function
D3
R
2
C interface until initialization is com-
D2
R
Si5351A/B/C
D1
REVID[1:0]
R
D0
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