Si5351B-A-GU Silicon Laboratories Inc, Si5351B-A-GU Datasheet - Page 26

• Manufacturer Part Number: Si5351B-A-GU
• Description: Clock Generators & Support Products AnyRate 2 PLL 125MHz Clk w/VCXO&I2C 8out
• Manufacturer: Silicon Laboratories Inc
• Type: Any Frequency CMOS Clock Generatorr

Specifications of Si5351B-A-GU

• Mounting Style: SMD/SMT
• Max Input Freq: 0.008 MHz
• Max Output Freq: 133 MHz
• Number Of Outputs: 8
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Package / Case: QSOP-24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5351A/B/C
Reset value = 0000 0000
26
Register 1. Interrupt Status Sticky
Name
Bit
3:0
Type
7
6
5
4
Bit
SYS_INIT_STKY System Calibration Status Sticky Bit.
LOL_B_STKY
LOL_A_STKY
SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY
LOS_STKY
Reserved
Name
R/W
D7
The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig-
gered high. It remains high until cleared. Writing a 0 to this register bit will cause it to
clear.
0: No SYS_INIT interrupt has occurred since it was last cleared.
1: A SYS_INIT interrupt has occurred since it was last cleared.
PLLB Loss Of Lock Status Sticky Bit.
The LOL_B_STKY bit is triggered when the LOL_B bit (register 0, bit 6) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLL B interrupt has occurred since it was last cleared.
1: A PLL B interrupt has occurred since it was last cleared.
PLLA Loss Of Lock Status Sticky Bit.
The LOL_A_STKY bit is triggered when the LOL_A bit (register 0, bit 5) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLLA interrupt has occurred since it was last cleared.
1: A PLLA interrupt has occurred since it was last cleared.
CLKIN Loss Of Signal Sticky Bit (Si5351C Only).
The LOS_STKY bit is triggered when the LOS bit (register 0, bit 4) is triggered high. It
remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No LOS interrupt has occurred since it was last cleared.
1: A LOS interrupt has occurred since it was last cleared.
Leave as default.
R/W
D6
Preliminary Rev. 0.95
R/W
D5
R/W
D4
Function
R/W
D3
R/W
D2
R/W
D1
R/W
D0