CY28551LFXC Silicon Laboratories Inc, CY28551LFXC Datasheet
CY28551LFXC
Specifications of CY28551LFXC
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CY28551LFXC Summary of contents
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Universal Clock Generator for Intel, VIA, and SIS Features ® • Compliant to Intel CK505 • Selectable CPU clock buffer type for Intel selection • Selectable CPU frequencies • Universal clock to support Intel, SiS and VIA ...
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Pin Description Pin No. Name 1 PCI6_F 2 VDD48 3 **SEL24_48#/24_4 8M 4 **SEL1/48MHz 5 VSS48 6 VDDDOT 7,8 LINK0/DOT96T/SA TAT LINK1/DOT96C/SA TAC 9 VSSDOT 10 VDDSATA 11,12 PCIEX0[T/C]/SATA [T/C] 13 VSSSATA 14,15 PCIEX[T/C]1 16 VSSPCIE 17,18 PCIEX[T/C]2 19 VDDPCIE ...
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Pin Description (continued) Pin No. Name 45 VTT_PWRGD#/PD 46 SDATA 47 SCLK 48 VDDREF 49 XOUT 50 XIN 51 VSSREF 52 REF2 53 **FSC/REF1 54 **FSD/REF0 55 RESET_I#/SRESE T# 56 **DOC1 57 PCI0/**CLKREQ#B I/O,SE, 58 PCI1/**CLKREQ#A I/O,SE, 59 VSSPCI 60 ...
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Table 1. Frequency Select Table FSD FSC FSB FSA FSEL3 FSEL2 FSEL1 FSEL0 CPU0 266.6666667 266.6666667 100 133.3333333 133.3333333 100 200 166.6666667 166.6666667 100 ...
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Byte Count ...
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Control Registers Byte 0: Control Register 0 Bit @Pup Type R/W SATA/PCIEX[T/C]0 SATA/PCIEX[T/C]0 Output Enable Byte 1: ...
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Byte 2: Control Register 2 (continued) Bit @Pup Type R/W Byte 3: Control Register 3 Bit @Pup Type ...
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Byte 5: Control Register 5 Bit @Pup Type R/W Byte 6: Control Register 6 Bit @Pup Type ...
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Byte 7: Vendor ID (continued) Bit @Pup Type Byte 8: Control Register 8 Bit @Pup Type R/W ...
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Byte 10: Control Register 10 Bit @Pup Type R/W Byte 11: Control Register 11 Bit @Pup Type ...
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Byte 13: Control Register 13 Bit @Pup Type R/W Byte 14: Control Register 14 Bit @Pup Type R/W ...
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Byte 16: Control Register 16 Bit @Pup Type 7 0 R/W PCIE_DAF_N7 6 0 R/W PCIE_DAF_N6 5 0 R/W PCIE_DAF_N5 4 0 R/W PCIE_DAF_N4 3 0 R/W PCIE_DAF_N3 2 0 R/W PCIE_DAF_N2 1 0 R/W PCIE_DAF_N1 0 0 R/W PCIE_DAF_N0 ...
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Crystal Recommendations The CY28551 requires a parallel resonance crystal. Substi- tuting a series resonance crystal will cause the CY28551 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift ...
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Dynamic Frequency Dynamic Frequency – Dynamic Frequency (DF technique used to increase CPU frequency or SRC frequency dynami- cally from any starting value. The user selects the starting point, either by HW, FSEL, or DAF, then enables DF. ...
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Watchdog Timer The Watchdog timer is used in the system in conjunction with overclocking used to provide a reset to a system that has hung up due to overclocking the CPU and the Front side bus. The watchdog ...
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LOW value and held prior to turning off the VCOs and the crystal oscillator PD Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs must be held LOW on their ...
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CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for cleanly stopping and starting the CPU outputs while the rest of the clock generator continues to function. Note that the assertion and deassertion of this signal is absolutely ...
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VDD_A = 2.0V S0 Power Off FS_[D:A] VTT_PWRGD# PWRGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO Rev 1.1, Faburary 1, 2008 S1 VTT_PWRGD# = Low Delay > 0. VDD_A = off Normal ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD T /T XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V (SSC refers ...
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AC Electrical Specifications Parameter Description T 266 MHz CPUT and CPUC Absolute PERIODSSAbs Period, SSC T 333 MHz CPUT and CPUC Absolute PERIODSSAbs Period, SSC T 400 MHz CPUT and CPUC Absolute PERIODSSAbs Period, SSC T CPU0 to CPU1 SKEW ...
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AC Electrical Specifications Parameter Description T DOT96T and DOT96C Period PERIOD T DOT96T and DOT96C Absolute Period Measured at crossing point V PERIODAbs T DOT96T/C Cycle to Cycle Jitter CCJ L DOT96T/C Long Term Accuracy ACC T Long Term Jitter ...
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AC Electrical Specifications Parameter Description USB T Duty Cycle DC T Period PERIOD T Absolute Period PERIODAbs T USB High Time HIGH T USB Low Time LOW T /T Rising and Falling Edge Rate Cycle-to-cycle Jitter CCJ ...
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Test and Measurement Set-up For PCI/USB and 24M Single-ended Signals and Reference Figure 12 and Figure 13 show the test load configurations for the single-ended PCI, USB, 24M, and REF output signals ...
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The following diagrams show the test load configuration for the differential CPU and PCIEX outputs Figure 14. Differential Load Configuration for 0.7V Push Pull Clock ...
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... Figure 17. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) Figure 18. Single-ended Output Signals (for AC Parameters Measurement Ordering Information Part Number Lead-free CY28551LFXC 64-pin QFN CY28551LFXCT 64-pin QFN – Tape and Reel Rev 1.1, Faburary 1, 2008 Package Type CY28551 Product Flow Commercial, 0° to 85°C Commercial, 0° ...
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Package Diagram 64-Lead QFN LF64A(Type I) 64-Lead QFN LF64A(Type II E-PAD mm 5.4 5.4 ...
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Document History Page Document Title: CY28551 Universal Clock Generator for Intel, VIA, and SIS Orig. of REV. Issue Date Change 1.0 11/20/06 JMA 1.1 2/01/08 BEN While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. ...