CY28551LFXC Silicon Laboratories Inc, CY28551LFXC Datasheet - Page 15

• Manufacturer Part Number: CY28551LFXC
• Description: Clock Generators & Support Products Universal System Clk Intel AMD SiS Via
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28551LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.1, Faburary 1, 2008
Watchdog Timer
The Watchdog timer is used in the system in conjunction with
overclocking. It is used to provide a reset to a system that has
hung up due to overclocking the CPU and the Front side bus.
The watchdog is enabled by the user and if the system
completes its checkpoints, the system will clear the timer.
However, when the timer runs out, there will be a reset pulse
generated on the SRESET# pin for 20 ms that is used to reset
the system.
When the Watchdog is enabled (WD_EN = 1) the Watchdog
timer will start counting down from a value of Watchdog_timer
* time scale. If the Watchdog timer reaches 0 before the
WD_EN bit is cleared then it will assert the SRESET# signal
and set the Watchdog Alarm bit to ‘1’.
To use the watchdog, the SRESET# pin must be enabled by
sampling SRESET_EN pin LOW by VTTPWRGD# assertion
during system boot up.
If at any point during the Watchdog timer countdown the time
stamp or Watchdog timer bits are changed, the timer will reset
and start counting down from the new value.
After the Reset pulse, the watchdog will stay inactive until
either:
Watchdog Register Bits
The following register bits are associated with the Watchdog
timer:
Watchdog Enable – This bit (by default) is not set, which
disables the Watchdog. When set, the Watchdog is enabled.
Also, when there is a transition from LOW to HIGH, the timer
reloads. Default = 0, disable
Watchdog Timer – There are three bits (for seven combina-
tions) to select the timer value. Default = 000, the value '000'
is a reserved test mode.
Watchdog Alarm – This bit is a flag and when it is set, it
indicates that the timer has expired. This bit is not set by
default. When the bit is set, the user is allowed to clear. Default
= 0.
Watchdog Time Scale – This bit selects the multiplier. When
this bit is not set, the multiplier will be 250 ms. When set (by
default), the multiplier will be 3s. Default = 1
Watchdog Reset Mode – This selects the Watchdog Reset
Mode. When this bit is not set (by default), the Watchdog will
send a reset pulse and reload the recovery frequency
depending on the Watchdog Recovery Mode setting. When
set, it sends a reset pulse. Default = 0, Reset & Recover
Frequency.
Watchdog Recovery Mode – This bit selects the location to
recover from. One option is to recover from the HW settings
(already stored in SMBUS registers for readback capability)
and the second is to recover from a register called “Recovery
N”. Default = 0 (Recover from the HW setting)
Watchdog Autorecovery Enable – This bit is set by default and
the recovered values are automatically written into the
“Watchdog Recovery Register” and reloaded by the Watchdog
function. When this bit is not set, the user is allowed to write to
the “Watchdog Recovery Register”. The value stored in the
1. A new time stamp or watchdog timer value is loaded.
2. The WD_EN bit is cleared and then set again.
“Watchdog Recovery Register” will be used for recovery.
Default = 1, Autorecovery.
Watchdog Recovery Register – This is a nine-bit register to
store the watchdog N recovery value. This value can be written
by the Autorecovery or User depending on the state of the
“Watchdog Autorecovery Enable bit”.
Watchdog Recovery Modes
There are three operating modes that require Watchdog
recovery. The modes are Dial-A-Frequency (DAF), Dynamic
Clocking (DF), or Frequency Select. There are four different
recovery modes; the following sections list the operating mode
and the recovery mode associated with it.
Recover to Hardware M, N, O
When this recovery mode is selected, in the event of a
Watchdog timeout, the original M, N, and O values that were
latched by the HW FSEL pins at chip boot-up will be reloaded.
Autorecovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the M and N values stored in the Recovery
M and N registers will be reloaded. The current values of M
and N will be latched into the internal recovery M and N
registers by the WD_EN bit being set.
Manual Recovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the N value as programmed by the user in
the N recovery register, and the M value that is stored in the
Recovery M register (not accessible by the user), will be
restored. The current M value will be latched to M recovery
register by the WD_EN bit being set.
No Recovery
If no recovery mode is selected, in the event of a Watchdog
time out, the device will assert the SRESET# and keep the
current values of M and N
Software Reset
Software reset is a reset function that is used to send out a
pulse from the SRESET# pin. It is controlled by the
SW_RESET enable register bit. Upon completion of the
byte/word/block write in which the SW_RESET bit was set, the
device will send a RESET pulse on the SRESET# pin. The
duration of the SRESET# pulse will be the same as the
duration of the SRESET# pulse after a Watchdog timer time
out.
After the SRESET# pulse is asserted the SW_RESET bit will
be automatically cleared by the device.
PD Clarification
The VTT_PWRGD#/PD pin is a dual-function pin. During initial
power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal must be synchro-
nized internal to the device prior to powering down the clock
synthesizer. PD is also an asynchronous input for powering up
the system. When PD is asserted HIGH, all clocks must be
CY28551
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