CY2PP326AI Cypress Semiconductor Corp, CY2PP326AI Datasheet - Page 2

• Manufacturer Part Number: CY2PP326AI
• Description: Clock Drivers & Distribution 2.5V or 3.3V 1.5GHz IND
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2PP326AI

• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Clock Inputs: 2
• Output Logic Level: ECL, PECL
• Supply Voltage (max): +/- 3.465 V
• Supply Voltage (min): +/- 2.375 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07506 Rev.*D
Pin Definitions
Table 1. Function Table
Table 2. Clock Select Control
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP326. The agency name and relevant specification is
listed below in Table 3.
Table 3.
19,3
22,6
21,4
20,5
31,28,25
32,29,26
10,13,16
9,12,15
2,7,18,23,
1,8,11,14,17,24,27,30
OAE#
OEB#
SEL0,SEL1
JEDEC
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V
Control
V
and are between V
EE
Agency Name
SEL0
is connected to GND (0V) and V
0
0
1
1
Pin
0
0
00
Default
CC
and V
SEL1
QA(0–2), QX(0–2)# are active. Deassertion of OE#
can be asynchronous to the reference clock without
generation of output runt pulses.
QA(0–2), QX(0–2)are active. Deassertion of OE#
can be asynchronous to the reference clock without
generation of output runt pulses.
EE
0
1
0
1
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
.
OEA#,OEB#
SEL0,SEL1
CLK(0:1)#
CLK(0:1)
QA(0:2)#
QB(0:2)#
QA(0:2)
QB(0:2)
CC
Name
VCC
VEE
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
EE
QA(0:2) and QB(0:2)
Specification
CLK0 Routed to
is either –3.3V or –2.5V and V
QA(0:2)
QB(0:2)
I,PD/PU
+PWR
–PWR
0
I/O
I,PD
–
O
O
I
I
[1]
ECL/PECL True Differential Inputs.
ECL/PECL Complement Differential Inputs.
ECL/PECL Differential Outputs – Bank A.
ECL/PECL Differential Outputs – Bank B.
LVCMOS
LVCMOS
POWER
Type
GND
CC
[2]
is connected to GND (0V). In PECL mode (positive power supply mode),
See Table 2
QA(0:2) and QB(0:2)
CLK1 Routed to
Clock/Data Switch Select.
Output Enable.
Negative Power Supply.
Positive Power Supply.
QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can
be asynchronous to the reference clock without
generation of output runt pulses.
QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can
be asynchronous to the reference clock without
generation of output runt pulses.
QB(0:2)
QA(0:2)
–
Description
FastEdge™ Series
1:6 fanout of CLK1
Dual 1:3 buffer
Dual 1:3 buffer crossed
1:6 fanout of CLK0
1
Application Mode
CY2PP326
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