CY2PP326AI Cypress Semiconductor Corp, CY2PP326AI Datasheet - Page 4

• Manufacturer Part Number: CY2PP326AI
• Description: Clock Drivers & Distribution 2.5V or 3.3V 1.5GHz IND
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2PP326AI

• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Clock Inputs: 2
• Output Logic Level: ECL, PECL
• Supply Voltage (max): +/- 3.465 V
• Supply Voltage (min): +/- 2.375 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07506 Rev.*D
ECL DC Electrical Specifications
AC Electrical Specifications
Notes:
10. 50% duty cycle; standard load; differential operation
12. Output pulse skew is the absolute difference of the propagation delay times: | t
11. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
V
V
V
V
V
V
V
F
T
Vo
V
tsk
tsk
T
tsk
T
t
t
PDL
PLD
Parameter
Parameter
CLK
PD
PER
R
EE
CMR
OH
OL
IH
IL
PP
CMRO
data points
,T
(0)
(PP)
(P)
F
Negative Power Supply
Differential cross point voltage
Output High Voltage
Output Low Voltage
V
V
Input Voltage, High
Input Voltage, Low
Differential Input Voltage
Input Frequency
Propagation Delay CLKA or CLKB to
Output pair
Output Voltage (peak-to-peak; see Fig-
ure 2)
Output Common Voltage Range (typ.)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (rms)
Output Pulse Skew
Output Rise/Fall Time (see Figure 2)
Output disable time
Output enable time
EE
EE
= –3.3V ± 5%
= –2.5V ± 5%
C L K 1 /1 #
C L K 1 /1 #
C L K 0 /0 #
C L K 0 /0 #
S E L 0 /1
Description
Description
S E L 0 /1
[12]
Figure 1. Channel Cross Point Switch/Mux Configurations
S w i t c h
R e p e a t e r
[7]
R o u t e r O p t i o n s
[11]
[7]
–2.5V ± 5%, V
–3.3V ± 5%, V
Differential operation
I
I
Single-ended operation
Single-ended operation
Differential operation
50% duty cycle Standard load
< 1 GHz
< 1 GHz
660 MHz
660 MHz
660 MHz
660 MHz
660 MHz 50% duty cycle
Differential 20% to 80%
T = CLK period
T = CLK period
OH
OL
B a n k A
B a n k A
B a n k B
B a n k B
= –5 mA
= –30 mA
[10]
[10]
[10]
[10]
[10]
PLH
Condition
Condition
[8]
, See Figure 3
, See Figure 3
– t
[8]
CC
CC
PHL
= 0.0V
= 0.0V
|.
C L K 0 /0 #
C L K 1 /1 #
C L K 0 /0 #
C L K 1 /1 #
S p l i t t e r O p t i o n s
S p l i t t e r B
2.5T + T
3.0T + T
S p l i t t e r A
V
–1.945
–2.625
–3.465
–1.995
–1.995
–1.165
EE
–1.25
0.375
Min.
Min.
0.08
0.1
–
–
–
–
–
–
+ 1.2
FastEdge™ Series
PD
PD
V
[9]
CC
– 1.425
S E L 0 /1
3.5T + T
4.0T + T
B a n k A
B a n k A
B a n k B
B a n k B
S E L 0 /1
–0.880
–2.375
–3.135
–1.625
Max.
Max.
1200
–0.7
–1.5
–1.3
CY2PP326
250
1.3
1.5
2.8
0.3
0V
50
75
–
PD
PD
[9]
Page 4 of 9
Unit
GHz
Unit
ps
ps
ps
ps
ps
ns
ns
ns
V
V
V
V
V
V
V
V
V