LX256V-35FN484C Lattice, LX256V-35FN484C Datasheet - Page 18

• Manufacturer Part Number: LX256V-35FN484C
• Description: Analog & Digital Crosspoint ICs 256 I/O Switch Matrix, 3.3V, SERDES, 3.5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX256V-35FN484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 12. ispGDX2 FIFO Signals
Read Clock and Read Enable are the same as the Clock and Clock Enable signals of the input registers of the
associated MRB. These registers are used to register the FIFO outputs, and in modes that utilize the FIFO are con-
figured to use the same clock and clock enable signals. The Write Clock is selected from one of the GCLK/CE sig-
nals or the RECCLK (Recovered Clock) signal from the associated SERDES. The Write Enable is selected from
one of the local MRB product term CLK/CE signals. All FIFO operations occur on the rising edge of the clock
although clock polarity of these signals can be programmed.
The flags from the FIFO, FULL, EMPTY and STRDb (Start Read) are each fed via a MUX in the MRB to an I/O
buffer. The STRDb (half full) signal is used in conjunction with SERDES. STRDb is an active low signal, the signal
is inactive (high) on FIFO RESET. After the FIFO reset when the FIFO contains data in five memory locations, at
the following write clock transition the STRDb becomes active (low). Note, if the Read Clocks arrive before writing
the sixth location, it may take longer than five write clocks before the STRDb becomes active. When the FIFO has
data in the first six locations, at the next write clock transition the STRDb becomes inactive (high). Again, if the
Read Clocks arrive before writing the seventh location, the STRDb may stay active for longer than one write clock
period, even if the FIFO contains data in less than five locations. After this event, the STRDb stays inactive until the
FIFO is RESET again. STRDb does not become active again even if less than six memory locations are occupied
in the FIFO. It is the user’s responsibility to monitor the FULL and EMPTY signals to avoid data underflow/overflow
and to take appropriate actions.
Figure 13 shows how the FIFO is connected between the I/O banks and the GDX Blocks in FIFO mode. For more
information on the FIFO, please refer to Lattice technical note number TN1020, sysHSI Usage Guidelines .
Power-on Reset (PORb)
FIFO Reset (FIFORSTb)
Global Reset (RESETb)
Read Clock (RCLK)
Read Enable (RE)
Data Out (DOUT)
10
15
10x15
FIFO
10
Data In (DIN)
Write Clock (WCLK)
Write Enable (WE)
Full (FULL)
Empty (EMPTY)
Start Read (STRDb)
ispGDX2 Family Data Sheet