LX256V-35FN484C Lattice, LX256V-35FN484C Datasheet - Page 54

• Manufacturer Part Number: LX256V-35FN484C
• Description: Analog & Digital Crosspoint ICs 256 I/O Switch Matrix, 3.3V, SERDES, 3.5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX256V-35FN484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
Lattice Semiconductor
ispGDX2-64 Power Supply and NC Connections
HSImA_TXDw, HSImB_ TXD
HSImA_RXDw, HSImB_ RXD
Source Synchronous Functions
SS_SCLKIN0P, SS_SCLKIN1P
SS_SCLKIN0N, SS_SCLKIN1N
SS_CLKOUT0N, SS_CLKOUT1P
SS_CLKOUT0N, SS_CLKOUT1N
CAL
1. m, w, x, y and z are variables.
2. Not on ispGDX2-64
Signal Names
w
w
1
(Continued)
V
V
V
V
V
V
V
V
V
V
V
GND
GND
1. All grounds must be electrically connected at the board level.
2. Pin orientation A1 starts from the upper left corner of the top
CC
CCO0
CCO1
CCO2
CCO3
CCO4
CCO5
CCO6
CCO7
CCJ
CCP0
side view with alphabetical order ascending vertically and
numerical order ascending horizontally.
Signal
P0
Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.
Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.
Input – Positive sense clock input for Source Synchronous group A, B.
Input – Negative (minus) sense clock input for Source Synchronous group A, B.
Output – Positive sense clock output for Source Synchronous group A, B.
Output – Negative (minus) sense clock output for Source Synchronous group A, B.
Input – Initiates source synchronous calibration sequence.
A1, K10
J7
F10
E10
B7
B4
E1
F1
K4
K1
G6
G5
A10, B9, C8, E6, E5, F6, F5, H3, J2
ispGDX2-64 (100-Ball fpBGA)
51
Description
1
ispGDX2 Family Data Sheet
2