LAN9215I-MT SMSC, LAN9215I-MT Datasheet
LAN9215I-MT
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LAN9215I-MT Summary of contents
Page 1
... Reduced Power Modes — Numerous power management modes — Wake on LAN* — Magic packet wakeup* — Wakeup indicator event signal — Link Status Change SMSC LAN9215i LAN9215i 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Single chip Ethernet controller — ...
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... LAN9215i-MT FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2010 SMSC or its subsidiaries. All rights reserved. ...
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... Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.10 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10.1 Power-On Reset (POR 3.10.2 Hardware Reset Input (nRESET 3.10.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.10.4 Soft Reset (SRST 3.10.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.11 MII Interface - External MII Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SMSC LAN9215i 3 DATASHEET Revision 2.7 (03-15-10) ...
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... Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1 Register Nomenclature and Access Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 System Control and Status Registers Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 4 DATASHEET Datasheet SMSC LAN9215i ...
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... Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.5.13 PHY Special Control/Status 118 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 119 SMSC LAN9215i 5 DATASHEET Revision 2.7 (03-15-10) ...
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... Worst Case Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.1 100-TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 6 DATASHEET Datasheet SMSC LAN9215i ...
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... Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 6.5 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 6.6 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 6.7 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 6.8 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 8.1 100 Pin TQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SMSC LAN9215i 7 DATASHEET Revision 2.7 (03-15-10) ...
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... Table 5.6 MAC CSR Register Map Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 5.8 LAN9215i PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 6 ...
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... The LAN9215i also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9215i can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Compatibility with First-generation LAN9118 Family Devices The LAN9215i is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers written for these products will work with the LAN9215i. However, in order to support HP Auto-MDIX, other components such as the magnetics and the passive components around the magnetics need to change, and supporting these changes does require a minor PCB change. A reference design for the LAN9215i will be available on SMSC’ ...
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... PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN9215i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. ...
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... Serial EEPROM Interface A serial EEPROM interface is included in the LAN9215i. The serial EEPROM is optional and can be programmed with the LAN9215i MAC address. The LAN9215i can optionally load the MAC address automatically after power-on reset, hardware reset, or soft reset. ...
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... The LAN9215i can be interfaced to either Big-Endian or Little-Endian processors. 1.13 External MII Interface The LAN9215i also supports the ability to interface to an external PHY device. This interface is compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the MII interface and associated signals, please refer to Switching," ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support SMSC LAN9215i 100 PIN TQFP Figure 2.1 Pin Configuration (Top View) 14 DATASHEET Datasheet 50 D10 49 D11 48 VDD_IO 47 GND_IO 46 D12 45 D13 44 D14 43 D15 42 VDD_IO 41 GND_IO 40 TX_CLK 39 TXD0 38 TXD1 37 TXD2 36 TXD3 35 VDD_IO 34 GND_IO 33 COL 32 CRS 31 MDC 30 MDIO** 29 RX_DV 28 VDD_IO 27 GND_IO 26 RX_CLK SMSC LAN9215i ...
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... LAN9215i when reduced power state Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9215i when reduced power state. O8/OD8 1 Programmable Interrupt request. Programmable polarity, source and buffer types. ...
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... GPO signal RX_DV/RX_CLK monitor, the EECS pin is deasserted never unintentionally access the serial EEPROM. This signal cannot function as a general-purpose input. Note: When the EEPROM interface is not used, the EECLK pin must be left unconnected. 16 DATASHEET Datasheet DESCRIPTION SMSC LAN9215i ...
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... If nRESET is left unconnected, the LAN9215i will rely on its internal power-on reset circuitry. Note: O8/OD8 1 When programmed to do so, is asserted when the LAN9215i detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note Enables Auto-MDIX ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9215i detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then ...
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... RX_ER Collision Detect: COL Receive Data[3:0] RXD[3:0] Carrier Sense CRS Receive Data RX_DV Valid: SMSC LAN9215i BUFFER NUM TYPE PINS P 1 +1.8V Power from the internal PLL regulator. This pin must be connected to a 10uF capacitor (<2 Ohm ESR), in parallel with a 0.01uF capacitor to ground ...
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... Management Data Clock: When SMI_SEL = 1, this pin is the MII management data clock. (PD) When SMI_SEL=0, this pin is driven low. See Note 2.3. Note: See "HW_CFG—Hardware Configuration Register" SMI_SEL. 20 DATASHEET Datasheet DESCRIPTION Section 5.3.9, for more information on Section 5.3.9, for more information on SMSC LAN9215i ...
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... GND_IO 44 20 VDD_IO 45 21 TX_EN 46 22 RXD1 47 23 RXD2 48 24 RXD3 49 25 RX_ER 50 SMSC LAN9215i PIN PIN NAME NUM PIN NAME RX_CLK 51 D9 GND_IO 52 D8 VDD_IO 53 D7 RX_DV 54 GND_IO MDIO 55 VDD_IO MDC 56 D6 CRS 57 D5 COL 58 D4 GND_IO 59 D3 VDD_IO 60 GND_IO ...
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... PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Table 2.8 Buffer Types DESCRIPTION 22 DATASHEET Datasheet SMSC LAN9215i ...
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... Generation of control frames Interface to the internal PHY and optional external PHY. The transmit and receive data paths are separate within the LAN9215i from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. ...
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... Flow Control The LAN9215i Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time. A Pause ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9215i address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9215i Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9215i packet filter function performs an imperfect address filtering against the hash table ...
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... The Diagram shown in up frame filter register’s structure. Note 3.1 Wake-up frame detection can be performed when the LAN9215i is in the power states. In the D0 state, wake-up frame detection is enabled when the WUEN bit is set. Note 3.2 Wake-up frame detection, as well as Magic Packet detection, is always enabled and cannot be disabled when the device enters the D1 state ...
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... FILTER I BYTE MASK DESCRIPTION Table 3.4 FILTER i COMMANDS Table 3.5 describes the Filter i Offset bit fields. 28 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter I command register. SMSC LAN9215i ...
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... MAC examines receive data for a Magic Packet. The LAN9215i can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9215i is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. ...
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... EEPROM is not detected the responsibility of the host LAN Driver to set the IEEE addresses. The LAN9215i EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation ...
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... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9215i will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. ...
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... E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. Please refer to the E2P_CMD register description in page 95 for E2P_CMD field settings for each command. SMSC LAN9215i EEPROM Read Idle Write Data Register ...
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... EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 3.3 EEPROM ERASE Cycle Figure 3.4 EEPROM ERAL Cycle 34 DATASHEET Datasheet t CSL t CSL SMSC LAN9215i ...
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... Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN9215i Figure 3.5 EEPROM EWDS Cycle 1 ...
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... EEDIO (OUTPUT EEDIO (INPUT) Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 3.7 EEPROM READ Cycle Figure 3.8 EEPROM WRITE Cycle Figure 3.9 EEPROM WRAL Cycle 36 DATASHEET Datasheet t CSL CSL D0 t CSL D0 SMSC LAN9215i ...
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... Refer to Section 6.9, "EEPROM Timing," on page 129 3.9 Power Management The LAN9215i supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.9.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management States,” ...
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... In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_CTRL register can be read to determine which LAN9215i device is driving the PME signal. When the LAN9215i power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the LAN9215i to the D0 state. Components,” on page 132 page 132, shows the power consumption values for each power state ...
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... A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9215i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9215i can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.12 After a POR, nRESET or SRST, the LAN9215i will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC ...
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... Resume Reset Timing After issuing a write to the BYTE_TEST register to wake the LAN9215i from a power-down state, the READY bit in PMT_CTRL will assert (set High) within 2ms. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If the software driver polls this bit and it is not set within 100ms, then an error condition occurred ...
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... The LAN9215i Receiver must be halted. The halting of the LAN9215i receiver must be complete. The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks to the LAN9215i internal logic for both the internal PHY, and the external MII interface. The host must wait a period of time not less than 5 cycles of the slowest operating clock before executing the next step in this procedure ...
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... Enable the LAN9215i transmitter. Enable the LAN9215i receiver. The process is complete. The LAN9215i is now operational using the newly selected MII device. The above procedure must be repeated each time the MII port is switched. The procedure is identical when switching from internal PHY to external MII, or vice-versa. ...
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... External PHY to a Stable State 2 Halt Transmitter 3 TX Stopped? YES 4 Halt Receiver 5 RX Stopped? YES Set PHY_CLK_SEL 6 to 10b 7 Clocks Halted? YES SMSC LAN9215i 8 EXT_PHY_SEL to Desired MII Port 9 PHY_CLK_SEL to Desired MII Port Figure 3.11 MII Switching Procedure 45 DATASHEET Set Set Clocks ...
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... When a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. The LAN9215i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9215i is operating in a system that always performs multi-word bursts ...
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... TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32- bit values that are used by the LAN9215i in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure ...
Page 48
... TX data FIFO usage. Please refer to "Calculating Actual TX Data FIFO Usage," on page 52 actual TX data FIFO usage. Note 3.15 The LAN9215i host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. ...
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... This value, along with the Buffer End Alignment field, is read and checked by the LAN9215i and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9215i of the cumulative buffer sizes for a given packet. ...
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... Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Table 3.12 TX Command 'B' Format DESCRIPTION Table 3.13, "TX DATA Start Table 3.13 TX DATA Start Offset 11 10 D[31:24] D[23:16] 50 DATASHEET Datasheet Offset", shows the 01 00 D[15:8] D[7:0] SMSC LAN9215i ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9215i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 52 DATASHEET Datasheet SMSC LAN9215i ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Figure 3.14, "TX Example 1" how data is passed to the TX data FIFO. Note 3.16 The LAN9215i host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. atomic 16-bit transactions. Ethernet Controller ...
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... Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3.15 TX Example 2 54 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 183-Byte Payload Data NOTE: Extra bytes between buffers are not transmitted SMSC LAN9215i ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9215i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9215i is operating in a system that always performs multi-DWORD bursts ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support init Idle RX Interrupt Read RX Status DWORD Not Last Packet Read RX Packet init Read RX_FIFO_ INf Valid Status DWORD Read RX Status DWORD Not Last Packet Last Packet Read RX Packet 56 DATASHEET Datasheet SMSC LAN9215i ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9215i receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
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... RX status FIFO, to ascertain the data size and any error conditions. Host Read Order Last Note 3.17 The LAN9215i host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. 3.13.3 RX Status Format ...
Page 59
... If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9215i DESCRIPTION 59 DATASHEET Revision 2.7 (03-15-10) ...
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... Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 60 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Table 4.1. Each 4-bit data-nibble SMSC LAN9215i ...
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... INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV SMSC LAN9215i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 0111 ...
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... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 62 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID SMSC LAN9215i ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN9215i 100M PLL 25MHz 4B/5B ...
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... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 64 DATASHEET Datasheet SMSC LAN9215i ...
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... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. SMSC LAN9215i 65 DATASHEET Revision 2.7 (03-15-10) ...
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... Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 66 DATASHEET Datasheet SMSC LAN9215i ...
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... Parallel Detection If the LAN9215i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
Page 68
... Mbps Note 4.1 The LAN9215i 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, the internal CRS stays low and does not indicate carrier detection ...
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... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9215i is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. ...
Page 70
... Chapter 5 Register Description The following section describes all LAN9215i registers and data ports. Note: The LAN9215i host bus interface supports 16-bit bus transfers; internally, all data paths are 32- bits wide. Figure 5.1 transactions. FCh B4h B0h ACh A8h A4h A0h 50h ...
Page 71
... LAN9215i registers accordingly. 5.2 RX and TX FIFO Ports The LAN9215i contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data ...
Page 72
... Automatic Flow Control Configuration EEPROM Command EEPROM Data Reserved for future use 72 DATASHEET Datasheet DEFAULT See Page 73. 00000000h 00000000h 00000000h - 87654321h 48000000h 00000000h 00000000h 00050000h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh - 00000000h - 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - SMSC LAN9215i ...
Page 73
... IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently deasserted. This bit has no effect on any internal interrupt status bits. 7-5 Reserved SMSC LAN9215i 50h Size: DESCRIPTION 54h Size: ...
Page 74
... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 74 DATASHEET Datasheet TYPE DEFAULT R/W 0 NASR RO - R/W 0 NASR SMSC LAN9215i ...
Page 75
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9215i. The LAN9215i will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 76
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 76 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9215i ...
Page 77
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9215i 5Ch Size: DESCRIPTION 77 DATASHEET 32 bits TYPE DEFAULT R R/W ...
Page 78
... RX Status FIFO Level interrupt (RSFL) will be generated. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 64h Size: DESCRIPTION 68h Size: DESCRIPTION 78 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9215i ...
Page 79
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9215i will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 80
... TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9215i Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero. ...
Page 81
... MDIO and MDC signals are driven low. When this bit is cleared, the external MIDIO signal is tri-stated, and the MDC signal is driven low. Note: This bit does not control the multiplexing of other MII signals. SMSC LAN9215i 74h Size: for details on stopping the transmitter and receiver. ...
Page 82
... The internal RX_CLK and TX_CLK signals must be running for a proper software reset. Please refer to Section 6.8, "Reset Timing," on page 128 The LAN9215i must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. ...
Page 83
... SMSC LAN9215i Table 5.3 Valid TX/RX FIFO Allocations TX STATUS FIFO RX DATA FIFO SIZE (BYTES) 512 512 512 512 512 512 512 512 512 512 512 512 512 83 DATASHEET RX STATUS FIFO ...
Page 84
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9215i moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 85
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9215i Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO ...
Page 86
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9215i Note: The LAN9215i must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS 31:14 ...
Page 87
... Device Ready (READY). When set, this bit indicates that LAN9215i is ready to be accessed. This register can be read when LAN9215i is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9215i has stabilized and is fully alive ...
Page 88
... Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 88 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 0000 RO - SMSC LAN9215i ...
Page 89
... Timer is put into the run state. When cleared, the GP Timer is halted. On the transition of this bit the GPT_LOAD field will be preset to FFFFh. 28-16 Reserved 15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. SMSC LAN9215i DESCRIPTION Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 ...
Page 90
... This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN9215i. The LAN9215i always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 91
... BITS 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9215i 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION ...
Page 92
... MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support A4h Size: DESCRIPTION A8h Size: DESCRIPTION 92 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN9215i ...
Page 93
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9215i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 ...
Page 94
... BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9215i will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9215i is operating in full-duplex mode. ...
Page 95
... Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN9215i B0h Size: DESCRIPTION 95 DATASHEET 32 bits ...
Page 96
... Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION [28] OPERATION 0 0 READ 0 1 EWDS 1 0 EWEN 1 1 WRITE 0 0 WRAL 0 1 ERASE 1 0 ERAL 1 1 Reload 96 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9215i ...
Page 97
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM. BITS 31-8 Reserved 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN9215i DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 97 ...
Page 98
... Multicast Hash Table High Multicast Hash Table Low MII Access MII Data Flow Control VLAN1 Tag VLAN2 Tag Wake-up Frame Filter Wake-up Control and Status 98 DATASHEET Datasheet DEFAULT 00040000h 0000FFFFh FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h SMSC LAN9215i ...
Page 99
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN9215i 1 Attribute: 00040000h Size: DESCRIPTION 99 ...
Page 100
... BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9215i will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 101
... Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. 1-0 Reserved SMSC LAN9215i DESCRIPTION BOLMT Value # Bits Used from LFSR Counter 2’b00 2’ ...
Page 102
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9215i device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. ...
Page 103
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9215i device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 104
... Lower 32 bits of the 64-bit Hash Table Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 104 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN9215i ...
Page 105
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9215i to read or write any of the MII PHY registers. ...
Page 106
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9215i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 107
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN9215i 9 Attribute: 00000000h ...
Page 108
... Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support B Attribute: 00000000h Size: DESCRIPTION C Attribute: 00000000h Size: DESCRIPTION 108 DATASHEET Datasheet WO 32 bits R/W 32 bits SMSC LAN9215i ...
Page 109
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9215i PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 110
... The default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 0 Size: DESCRIPTION 110 DATASHEET Datasheet 16-bits TYPE DEFAULT RW/ See Note 5.1 RW See Note 5 RW/ SMSC LAN9215i ...
Page 111
... Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. 5.5.3 PHY Identifier 1 Index (In Decimal): BITS 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN9215i 1 Size: DESCRIPTION 2 Size: DESCRIPTION 111 DATASHEET ...
Page 112
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5.2) 112 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0xC0C3h RO RO 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.3 R/W 1 R/W See Note 5.3 R/W See Note 5.3 R/W 00001 SMSC LAN9215i ...
Page 113
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9215i 5 Size: DESCRIPTION 113 DATASHEET 16-bits TYPE DEFAULT ...
Page 114
... The default value of this bit will vary dependant on the current link state of the line. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 6 Size: DESCRIPTION 17 Size: DESCRIPTION 114 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT See Note 5 SMSC LAN9215i ...
Page 115
... Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9215i in this mode. 111 All capable. Auto-negotiation enabled. Note 5.5 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto- negotiated speed and duplex. ...
Page 116
... XPOL: Polarity state of the 10Base- Normal polarity 1 - Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 27 Size: DESCRIPTION 116 DATASHEET Datasheet 16-bits MODE DEFAULT RW, 0 NASR XXXXb SMSC LAN9215i ...
Page 117
... The default value of this bit will vary dependant on the current link state of the line. 5.5.12 Interrupt Mask Index (In Decimal): BITS 15-8 Reserved. Write as 0; ignore on read. 7-0 Mask Bits interrupt source is enabled 0 = interrupt source is masked SMSC LAN9215i 29 Size: DESCRIPTION 30 Size: DESCRIPTION 117 DATASHEET ...
Page 118
... See Table 2.2, “Default Ethernet Settings,” on page Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 31 Size: DESCRIPTION 118 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 000b 0000010b RO See Note 5.7 RO 00b 15, for default settings. SMSC LAN9215i ...
Page 119
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9215i before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 120
... MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 165 165 165 0 165 165 165 165 165 0 165 330 165 165 165 165 330 0 165 165 165 165 165 120 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 165NS) CYCLE SMSC LAN9215i ...
Page 121
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9215i, and the subsequent indication of the expected change in the control register values. ...
Page 122
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 6.1 PIO Read Cycle Timing Table 6.3 PIO Read Timing and t must be extended using wait states to meet the t csl 122 DATASHEET Datasheet MIN TYP MAX UNITS 165 133 minimum. cycle SMSC LAN9215i ...
Page 123
... Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9215i Figure 6.2 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing ...
Page 124
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9215i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215i ...
Page 125
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9215i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215i ...
Page 126
... PIO Writes PIO writes are used for all LAN9215i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] nCS, nWR Data Bus Note: The “ ...
Page 127
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9215i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9215i ...
Page 128
... Output Drive after nRESET rising Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support T6.1 T6.2 T6.3 T6.4 Figure 6.7 Reset Timing Table 6.9 Reset Timing MIN TYP MAX 200 200 10 16 128 DATASHEET Datasheet UNITS NOTES SMSC LAN9215i ...
Page 129
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9215i: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK ...
Page 130
... Note: Apply and remove power to all power supply pins simultaneously, including the Ethernet magnetics. Do not apply power to individual supply pins without the others. **Proper operation of the LAN9215i is guaranteed only within the ranges specified in this section. Revision 2.7 (03-15-10) 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support (Note 7 ...
Page 131
... Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9215i in various modes of operation. All of these values are preliminary. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD: ...
Page 132
... Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9215i, including the power dissipated by the magnetics and other passive components. All of these values are preliminary. Please refer to the SMSC application note AN14.9 - “Migrating from LAN9115 to the LAN9215”, that can be found on SMSC’ ...
Page 133
... I/O Supply Current +3.3V Analog Supply Current Reference Supply Current Note: Above values do not include the supply current for the magnetics. Based on the recommended implementation, the maximum supply current needed for the magnetics is 108mA. SMSC LAN9215i SUPPLY NAME MAX VREG 69 ...
Page 134
... DC Electrical Specifications This section details the DC electrical specifications of the LAN9215i I/O buffers. The electrical specifications in this section are valid over the voltage range and the temperature range specified in Section 7.2, "Operating PARAMETER SYMBOL I Type Input Buffer Low Input Level V ILI ...
Page 135
... Measured differentially. Table 7.6 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. SMSC LAN9215i MIN TYP MAX -0.3 0.5 1.4 3.6 input leakage for the entire device. This value should be divided by IN MAX to calculate per-pin leakage ...
Page 136
... Clock Circuit The LAN9215i can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9215i shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 137
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN9215i MAX REMARKS 1.60 Overall Package Height 0 ...
Page 138
... Also added note stating “When both symmetric PAUSE and asymmetric PAUSE support are advertised, the device will only be configured to, at most, one of the two settings upon auto-negotiation completion.” 138 DATASHEET Datasheet CORRECTION SMSC LAN9215i ...
Page 139
... Configurationon (10-22-07) page 14 EECLK pin description in Chapter 2 Pin Description and Configurationon page 14 SMSC LAN9215i Added note: “When wake-up frame detection is enabled via the WUEN bit of the and Section 5.4.1, up Control and Status up frame will wake-up the device despite the state of the Disable Broadcast Frame (BCAST) bit in the MAC_CR— ...